81341 datasheet(28/89 Pages) INTEL

28 / 89 page

Intel® 81341 and 81342—Package Information

Datasheet

December 2007

Order Number: 315038-003US

Table 10. Miscellaneous Signals

Name

Count

Type

Description

TCK

Test Clock provides clock input for IEEE 1149.1 Boundary Scan

Testing (JTAG). State information and data are clocked into the

device on the rising clock edge, and data is clocked out on the

falling clock edge.

TDI

Sync (T)

Test Data Input is the JTAG serial input pin. TDI is sampled on the

rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of

the Test Access Port. This signal has a weak internal pull-up to

ensure proper operation when this pin is not being driven.

TDO

Sync (T)

Rst (T)

Test Data Output is the serial output pin for the JTAG feature. TDO

is driven on the falling edge of

TCK during the SHIFT-IR and

SHIFT-DR states of the Test Access Port. At other times,

TDO

floats. The behavior of

TDO is independent of other resets.

TRST#

Async

ActLow

Test Reset asynchronously resets the Test Access Port controller

function of IEEE 1149 Boundary Scan Testing (JTAG). This pin has

a weak internal pull-up.

Note: This pin must be tied low when not used.

TMS

Sync (T)

Test Mode Select is sampled on the rising edge of

TCK to select

the operation of the test logic for IEEE 1149 Boundary Scan

testing. This pin has a weak internal pull-up.

106

I/O

No Connect: Pins have no usable function and must not be

connected to any signal, power, or ground.

P_RST#

Async

ActLow

Cold Reset is used to asynchronously reset the I/O processor

when it is low. This signal must be asserted whenever the power

supplies are outside of the specified ranges.

• Registers are reset to default values.

• Pins are driven to known states.

• Sticky configuration bits are reset.

WARM_RST#

Async

ActLow

Warm Reset is the same as a cold reset, except sticky

configuration bits are not reset. This pin should only be used when

the sticky bit functionality is required. In this scenario, the

WARM_RST# pin must be tied to the system reset PCI_RST#

signal while the P_RST# pin can be tied to the system power good

signal. If the sticky bit functionality is not required, the

WARM_RST# pin should not be used and must be tied to Vcc.

When the PCI Express interface is used as an endpoint, the PCI

Express inband Hot Reset Mechanism can also be used to provide

the sticky bit functionality.

Note: Driving WARM_RST# using any other methods than

suggested above may result in unpredictable behavior of

the device.

THERMDA

Thermal Diode Anode is the anode of the thermal diode.

THERMDC

Thermal Diode Cathode is the cathode of the thermal diode.

PUR1

Pull-Up Required 1: This pin must be pulled up to

CC3P3

with an

external 8.2K ohm 5%, 1/16 W resistor for proper operation.

Total

116

81341 Datasheet(PDF) 28 Page - Intel Corporation

81341 Datasheet(HTML) 28 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

Datasheet Download

Link URL