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R27 Datasheet(PDF) 89 Page - Renesas Technology Corp |
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R27 Datasheet(HTML) 89 Page - Renesas Technology Corp |
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89 / 487 page ![]() R8C/26 Group, R8C/27 Group 7. Programmable I/O Ports Rev.2.10 Sep 26, 2008 Page 70 of 453 REJ09B0278-0210 3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode. X: 0 or 1 NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. NOTE: 1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode. X: 0 or 1 NOTES: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. 2. Set the SSISEL bit in the PMR register to 0 (P3_3). 3. When the SOOS bit is set to 1 (N-channel open drain output) and BIDE bit is set to 0 (standard mode) in the SSMR2 register, this pin is set to N-channel open drain output. X: 0 or 1 NOTES: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. 2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 (N-channel open drain output). Table 7.23 Port P3_1/TRBO Register PD3 Timer RB Setting Function Bit PD3_1 − Setting value 0 Other than TRBO usage conditions Input port(1) 1 Other than TRBO usage conditions Output port X Refer to Table 7.24 TRBO Pin Setting TRBO output Table 7.24 TRBO Pin Setting Register PINSR2 TRBIOC TRBMR Function Bit TRBOSEL TOCNT(1) TMOD1 TMOD0 Setting value 0 0 0 1 Programmable waveform generation mode 0 0 1 0 Programmable one-shot generation mode 0 0 1 1 Programmable wait one-shot generation mode 010 1 P3_1 output port Other than above Other than TRBO usage conditions Table 7.25 Port P3_3/INT3/SSI/TRCCLK Register PD3 PMR Clock Synchronous Serial I/O with Chip Select (Refer to Table 16.4 Association between Communication Modes and I/O Pins.) TRCCR1 INTEN Function(3) Bit PD3_3 IICSEL SSI output control SSI input control TCK2 TCK1 TCK0 INT3EN Setting value 0 X 0 0 Other than 101b 0 Input port(1) 1 X 0 0 Other than 101b 0 Output port 0 X 0 0 Other than 101b 1 INT3 input(1) 0 X 0 0 101 0 TRCCLK input(1) X 0 1 0 Other than 101b 0 SSI output(2) X 0 0 1 Other than 101b 0 SSI input(2) Table 7.26 Port P3_4/SDA/SCS/(TRCIOC) Register PD3 PMR ICCR1 SSMR2 Timer RC setting Function(2) Bit PD3_4 IICSEL ICE CSS1 CSS0 − Setting value 0 0 X 0 0 Other than TRCIOC usage conditions Input port(1) 1 0 0 0 Other than TRCIOC usage conditions 1 0 X 0 0 Other than TRCIOC usage conditions Output port 1 0 0 0 Other than TRCIOC usage conditions X X 0 0 0 Refer to Table 7.27 TRCIOC Pin Setting TRCIOC output 0 X 0 0 0 Refer to Table 7.27 TRCIOC Pin Setting TRCIOC input(1) X 0 X 1 0 Other than TRCIOC usage conditions SCS output X 0 X 1 1 Other than TRCIOC usage conditions SCS input(1) X 1 1 X X Other than TRCIOC usage conditions SDA input/output |
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