R28 datasheet(380/473 Pages) RENESAS

380 / 473 page

R8C/28 Group, R8C/29 Group

19. Flash Memory

Rev.2.10

Sep 26, 2008

Page 361 of 441

REJ09B0279-0210

19.4.5

Full Status Check

When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an

error. Therefore, checking these status bits (full status check) can be used to determine the execution result.

Table 19.6 lists the Errors and FMR0 Register Status. Figure 19.16 shows the Full Status Check and Handling

Procedure for Individual Errors.

NOTE:

1. The MCU enters read array mode when FFh is written in the second bus cycle of these commands.

At the same time, the command code written in the first bus cycle is disabled.

Table 19.6

Errors and FMR0 Register Status

FMR0 Register (Status

Error

Error Occurrence Condition

FMR07 (SR5) FMR06 (SR4)

Command

sequence

error

• When a command is not written correctly

• When invalid data other than that which can be written

in the second bus cycle of the block erase command is

written (i.e., other than D0h or FFh)(1)

• When the program command or block erase command

is executed while rewriting is disabled by the FMR02 bit

in the FMR0 register, or the FMR15 or FMR16 bit in the

FMR1 register.

• When an address not allocated in flash memory is input

during erase command input

• When attempting to erase the block for which rewriting

is disabled during erase command input.

• When an address not allocated in flash memory is input

during write command input.

• When attempting to write to a block for which rewriting

is disabled during write command input.

Erase error

• When the block erase command is executed but auto-

erasure does not complete correctly

Program error

• When the program command is executed but not auto-

programming does not complete.

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