R28 datasheet(253/473 Pages) RENESAS

253 / 473 page

R8C/28 Group, R8C/29 Group

15. Serial Interface

Rev.2.10

Sep 26, 2008

Page 234 of 441

REJ09B0279-0210

Figure 15.4

Registers U0BRG to U1BRG and U0MR to U1MR

UARTi Bit Rate Register (i = 0 or 1)

(1, 2, 3)

Symbol

Address

After Reset

U0BRG

00A1h

Undefined

U1BRG

00A9h

Undefined

Setting Range

NOTES:

Use the MOV instruction to w rite to this register.

Write to this register w hile the serial I/O is neither transmitting nor receiving.

00h to FFh

Function

Assuming the set value is n, UiBRG divides the count source by n+1

After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register.

UARTi Transmit/Receive Mode Register (i = 0 or 1)

Symbol

Address

After Reset

U0MR

00A0h

00h

U1MR

00A8h

00h

Bit Symbol

Bit Name

Function

NOTES:

3. Set bit 3 in the U1MR register to 0.

Do not set bits SMD2 to SMD0 in the U1MR register to any values other than 000b, 100b, 101b, and 110b.

SMD0

b3 b2 b1

Serial I/O mode select bits(2)

b2 b1 b0

0 0 0 : Serial interface disabled

0 0 1 : Clock synchronous serial I/O mode

1 0 0 : UART mode transfer data 7 bits long

1 0 1 : UART mode transfer data 8 bits long

1 1 0 : UART mode transfer data 9 bits long

Other than above : Do not set.

SMD1

b7 b6 b5 b4

Set the PD1_6 bit in the PD1 register to 0 (input).

SMD2

STPS

0 : 1 stop bit

1 : 2 stop bits

CKDIR

PRY

Odd/even parity select bit

Enable w hen PRYE = 1

0 : Odd parity

1 : Even parity

PRYE

Parity enable bit

0 : Parity disabled

1 : Parity enabled

Set to 0.

Internal/external clock select

bit(3)

0 : Internal clock

1 : External clock(1)

Stop bit length select bit

—

(b7)

Reserved bit

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