R28 datasheet(305/473 Pages) RENESAS

305 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 286 of 441

REJ09B0279-0210

Figure 16.27

ICIER Register

IIC bus Interrupt Enable Register

Symbol

Address

After Reset

ICIER

00BBh

00h

Bit Symbol

Bit Name

Function

NOTES:

0 : 0 is transmitted as acknow ledge bit in

receive mode.

1 : 1 is transmitted as acknow ledge bit in

receive mode.

b3 b2 b1

NAKIE

b7 b6 b5 b4

ACKE

STIE

ACKBT

ACKBR

Receive acknow ledge bit

0 : Acknow ledge bit received from

receive device in transmit mode is set to 0.

1 : Acknow ledge bit received from

receive device in transmit mode is set to 1.

Transmit acknow ledge

select bit

RIE

Receive interrupt enable

bit

0 : Disables receive data full and overrun

error interrupt request

1 : Enables receive data full and overrun

error interrupt request(1)

Acknow ledge bit judgment

select bit

0 : Value of receive acknow ledge bit is ignored

and continuous transfer is performed.

1 : When receive acknow ledge bit is set to 1,

continuous transfer is halted.

Stop condition detection

interrupt enable bit

0 : Disables stop condition detection interrupt

request

1 : Enables stop condition detection interrupt

request(2)

0 : Disables NACK receive interrupt request and

arbitration lost/overrun error interrupt request

1 : Enables NACK receive interrupt request and

arbitration lost/overrun error interrupt request(1)

NACK receive interrupt

enable bit

Set the STIE bit to 1 (enable stop condition detection interrupt request) w hen the STOP bit in the ICSR register is set

to 0.

0 : Disables transmit end interrupt request

1 : Enables transmit end interrupt request

An overrun error interrupt request is generated w hen the clock synchronous format is used.

TIE

Transmit interrupt enable

bit

0 : Disables transmit data empty interrupt request

1 : Enables transmit data empty interrupt request

TEIE

Transmit end interrupt

enable bit

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