R28 datasheet(306/473 Pages) RENESAS

306 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 287 of 441

REJ09B0279-0210

Figure 16.28

ICSR Register

IIC bus Status Register

(7)

Symbol

Address

After Reset

ICSR

00BCh

0000X000b

Bit Symbol

Bit Name

Function

NOTES:

7. When accessing the ICSR register continuously, insert one or more NOP instructions betw een the instructions to

access it.

STOP

Stop condition detection

flag(1)

When the stop condition is detected after the frame

is transferred, this flag is set to 1

The RDRF bit is set to 0 w hen reading data from the ICDRR register.

Bits TEND and TDRE are set to 0 w hen w riting data to the ICDRT register.

When tw o or more master devices attempt to occupy the bus at nearly the same time, if the I2C bus Interface

monitors the SDA pin and the data w hich the I2C bus Interface transmits is different, the AL flag is set to 1 and the

bus is occupied by another master.

RDRF

Receive data register

full(1,5)

When the 9th clock cycle of the SCL signal in the I2C

bus format occurs w hile the TDRE bit is set to 1, this

flag is set to 1.

This flag is set to 1 w hen the final bit of the transmit

frame is transmitted in the clock synchronous format.

No acknow ledge detection

flag(1,4)

This flag is enabled in slave receive mode of the I2C bus format.

Each bit is set to 0 by reading 1 before w riting 0.

NACKF

When no acknow ledge is detected from the receive

device after transmission, this flag is set to 1

When receive data is transferred from in registers

ICDRS to ICDRR , this flag is set to 1

TEND

Transmit end(1,6)

General call address

recognition flag(1,2)

When the general call address is detected, this flag

is set to 1.

Arbitration lost

flag/overrun error flag(1)

When the I2C bus format is used, this flag indicates

that arbitration has been lost in master mode. In the

follow ing cases, this flag is set to 1.(3)

• When the internal SDA signal and SDA pin

level do not match at the rise of the SCL signal

in master transmit mode

• When the start condition is detected and the

SDA pin is held “H” in master transmit/receive mode

This flag indicates an overrun error w hen the clock

synchronous format is used.

In the follow ing case, this flag is set to 1.

• When the last bit of the next data item is

received w hile the RDRF bit is set to 1

Slave address recognition

flag(1)

This flag is set to 1 w hen the first frame follow ing

start condition matches bits SVA0 to SVA6 in the

SAR register in slave receive mode. (Detect the

slave address and generate call address)

AAS

ADZ

b7 b6 b5 b4

The NACKF bit is enabled w hen the ACKE bit in the ICIER register is set to 1 (w hen the receive acknow ledge bit is

set to 1, transfer is halted).

TDRE

Transmit data empty(1,6)

In the follow ing cases, this flag is set to 1.

• Data is transferred from registers ICDRT to ICDRS

and the ICDRT register is empty

• When setting the TRS bit in the ICCR1

• When generating the start condition

(including retransmit)

• When changing from slave receive mode to

slave transmit mode

b3 b2

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