R8CL3AB datasheet(83/89 Pages) RENESAS

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RENESAS TECHNICAL UPDATE

TN-R8C-A002B/E

Date: Jul. 08, 2009

Page 2 of 8

2-1-1. Register Settings Related to the Clock Generation Circuit

2-1-1-1. High-Speed On-Chip Oscillator Control Register 0 (FRA0)

(1) Do NOT set FRA00 bit to 1 (high-speed on-chip oscillator on) [refer to Figure 2-1]

(2) Do NOT set FRA01 bit to 1 (high-speed on-chip oscillator selected as fOCO clock source) [refer to Figure 2-1].

The fOCO is a clock source of timer RA.

(3) Do NOT set FRA03 bit to 1 (fOCO-F divided by 128 selected as a clock source of fOCO128) [refer to Figure 2-1].

fOCO128 is used as an input-capture signal of timers RC and RD.

2-1-1-2. System Clock Control Register 3 (CM3)

(1) Do NOT set bits CM37 to CM36 bits to 10b (high-speed on-chip oscillator selected as CPU clock when the MCU exits

wait mode or stop mode) [refer to Figure 2-2].

2-1-1-3. High-Speed On-Chip Oscillator Control Register i (FRAi) (i = 1 to 7)

(1) Do NOT set the register related to the high-speed on-chip oscillator division select (FRA2) or registers related to

frequency adjustment (FRA1 and FRA3 to FRA7).

2-1-2. Register Settings Related to Timer RA

2-1-2-1. High-Speed On-chip Oscillator Control Register 0 (FRA0)

(1) Do NOT set the FRA01 bit to 1 (high-speed on-chip oscillator selected for the fOCO clock) [refer to Figure 2-1]. The

high-speed on-chip oscillator clock cannot be selected as the timer RA count source.

2-1-3 Register Settings Related to Timer RC

2-1-3-1. Timer RC Control Register 1 (TRCCR1)

(1) Do NOT set bits TCK2 to TCK0 to 110b (fOCO40M selected as the timer RC count source) [refer to Figure 2-3].

(2) Do NOT set bits TCK2 to TCK0 to 111b (fOCO-F selected as the timer RC count source) [refer to Figure 2-3].

2-1-3-2. High-speed On-Chip Oscillator Control Register 0 (FRA0)

(1) Do NOT set the FRA03 bit to 1 (fOCO-F divided by 128 selected as the fOCO 128 clock) [refer to Figure 2-1]. For the

timer RC input-capture function, fOCO-F divided by 128 cannot be selected for the input-capture trigger input of the TRCGRA

2-1-4. Register Settings Related to Timer RD

2-1-4-1. Timer RD Control Register 0, 1 (TRDCR0, TRDCR1)

(1) Do NOT set bits TCK2 to TCK0 to 110b (fOCO40M selected as the timer RD count source) [refer to Figure 2-4].

(2) Do NOT set bits TCK2 to TCK0 to 111b (fOCO-F selected as the timer RD count source) [refer to Figure 2-4].

2-1-4-2. High-speed On-Chip Oscillator Control Register 0 (FRA0)

(1) Do NOT set the FRA03 bit to 1 (fOCO-F divided by 128 cannot be selected for the input-capture trigger input of the

TRDGRA0 register [refer to Figure 2-1]. For the timer RD input-capture function, fOCO-F divided by 128 cannot be selected for

the input-capture trigger input of the TRDGRA register.

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