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IR3502 Datasheet(PDF) 12 Page - International Rectifier

Part # IR3502
Description  XPHASE3TM CONTROL IC
PDF  39 Pages
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

IR3502 Datasheet(HTML) 12 Page - International Rectifier

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IR3502
Page 12 of 39
July 28, 2009
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
Figure 6 Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 6. Its gain is
nominally 33 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop
feedback path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before
clipping. The output of the current sense amplifier is summed with the VDAC voltage and sent to the control IC and
other phases through an on-chip 3K
resistor connected to the IIN pin. The IIN pins of all the phases are tied
together and the voltage on the share bus represents the average current through all the inductors and is used by
the control IC for voltage positioning and current limit protection. The input offset of this amplifier is calibrated to +/-
1mV in order to reduce the current sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
calibration algorithm creates ripple on IIN bus with a frequency of fsw/(32*28) in a multiphase architecture.
Average Current Share Loop
Current sharing between the phases of the converter is achieved by the average current share loop in each phase
IC. The output of the current sense amplifier is compared with average current at the share bus. If current in a
phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of
the PWM ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average
current, the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its
duty cycle and output current. The current share amplifier is internally compensated; such that, the crossover
frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact.
CO
L
RL
RC
S
CC
S
VO
Current
Sense Amp
CSOUT
iL
vL
vC
S
c



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