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TLE5011 Datasheet(PDF) 23 Page - Infineon Technologies AG |
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TLE5011 Datasheet(HTML) 23 Page - Infineon Technologies AG |
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23 / 43 page ![]() TLE5011 Specification Final Data Sheet 23 V1.1, 2010-05 DATA Write Time ( t DATW ) During this time, the TLE5011 changes the data line, so the data are invalid. The DATA Write Time values are defined without a pull-up resistor. Pull-up Time Value ( t PU ) The value in Table 11 “SSC Timing Specification” on Page 23 is estimated at 60 ns. Figure 12 SSC Interface Timing Details - Worst-Case Specified Timing Note: The read window includes the sampling of the data bit. For SSC_FILT = 1, the 2-of-3 selection is already considered. Only the two last data values need to be equal. For SSC_FILT = 0, only one sample point is selected. Table 11 SSC Timing Specification Note: Timing must be calculated according to Table 10 “CLK Timing Specification” on Page 21 Parameter Symbol Limit Values Unit Notes min. typ. max. SSC Baud Rate fSSC - 2.0 2.1 1) 1) f CLK/2, synchronized to fCLK if fCLK = fCLK(max) Mbit / s CS Setup Time tCSs 3*t DIG+10 - - ns CS Hold Time tCSh 5*t DIG+10 - - ns CS off tCSoff 10*t DIG - - ns SSC inactive time SCK High tSCKh 5*t DIG - - ns SCK Low tSCKl 5*t DIG - - ns DATA Read Time (Data Valid Time) tDATr 6*t DIG-10 - 7*t DIG+10 ns SSC_FILT = 0 5*t DIG-10 - 7*t DIG+10 SSC_FILT = 1 DATA Write Time (Data Valid Time) 2) 2) t PU is the time generated by the pull-up resistor tDATw 6*t DIG+25 - 7*t DIG+50 + tPU ns DATA slope tDATs - 20 30 3) 3) Not tested ns Falling edge 4) 4) Internal slope control of falling edge for data bit transition from V H to VL. SCK SSC_FILT=0 SCK SSC_FILT=1 Wr tDATw MIN tDATw MAX tPU Wr tDATw MIN t DATw MAX tPU Earliest sample timepoint Rd tDATr MIN tDATr MAX Rd tDATr MIN tDATr MAX Earliest sample timepoint of second sample from 2 of 3 filter t SCKh t SCKl MIN |
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