PCA85232 datasheet(21/54 Pages) NXP

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PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

21 of 54

NXP Semiconductors

PCA85232

LCD driver for low multiplex rates

The PCA85232 includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. In the static drive mode, the bank-select command may request the contents

of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex

mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives

the provision for preparing display information in an alternative bank and to be able to

switch to it once it is assembled.

7.14 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

Table 14). The input bank selector functions independently to the output bank selector.

7.15 Blinker

The display blinking capabilities of the PCA85232 are very versatile. The whole display

can blink at frequencies selected by the blink-select command (see Table 15). The blink

frequencies are fractions of the clock frequency. The ratios between the clock and blink

frequencies depend on the blink mode in which the device is operating (see Table 6).

An additional feature is for an arbitrary selection of LCD elements to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. By means of the output bank selector, the displayed RAM

banks are exchanged with alternate RAM banks at the blink frequency. This mode can

also be specified by the blink-select command (see Table 15).

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD elements can blink selectively by changing the display RAM data at fixed time

intervals.

The entire display can blink at a frequency other than the nominal blinking frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 10).

7.16 Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

Table 6.

Blink frequencies

Assuming that fclk = 3.500 kHz.

Blink mode

Operating mode ratio

Blink frequency

off

blinking off

1~4.56 Hz

2~2.28 Hz

3~1.14 Hz

blink

clk

768

---------

blink

clk

1536

------------

blink

clk

3072

------------

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