PCA85232 datasheet(39/54 Pages) NXP

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PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

39 of 54

NXP Semiconductors

PCA85232

LCD driver for low multiplex rates

12.3 Cascaded operation

In large display configurations, up to 8 PCA85232 can be distinguished on the same

I2C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable

I2C-bus slave address (SA0).

When cascaded PCA85232 are synchronized, they can share the backplane signals from

one of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCA85232 of the cascade contribute

additional segment outputs but their backplane outputs are left open-circuit (see

Figure 29).

For display sizes that are not multiple of 640 elements, a mixed cascaded system can be

considered containing only devices like PCA85232 and PCA85133. Depending on the

application, one must take care of the software commands compatibility and pin

connection compatibility.

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCA85232. This synchronization is guaranteed after the Power-On Reset (POR). The

only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by

noise in adverse electrical environments, or by the definition of a multiplex mode when

PCA85232 with different SA0 levels are cascaded). SYNC is organized as an input/output

pin; the output selection being realized as an open-drain driver with an internal pull-up

resistor. A PCA85232 asserts the SYNC line at the onset of its last active backplane signal

and monitors the SYNC line at all other times. Should synchronization in the cascade be

lost, it will be restored by the first PCA85232 to assert SYNC. The timing relationship

between the backplane waveforms and the SYNC signal for the various drive modes of

the PCA85232 are shown in Figure 31.

When using an external clock signal with high frequencies (fclk(ext) > 4 kHz) it is

recommended to have an external pull-up resistor between pin SYNC and pin VDD (see

Table 19). This resistor should be present even when no cascading configuration is used!

When using it in a cascaded configuration, care must be taken not to route the SYNC

signal to close to noisy signals.

The contact resistance between the SYNC pads of cascaded devices must be controlled.

If the resistance is too high, the device will not be able to synchronize properly. This is

particularly applicable to COG applications. Table 21 shows the limiting values for contact

resistance.

Table 20.

Addressing cascaded PCA85232

Cluster

Bit SA0

Pin A1

Pin A0

Device

000

011

102

113

004

015

106

117

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