CDPD Wireless Modem Data Pump

FX949

© 1996 Consumer Microcircuits Limited

14

D/949/5

SYNC ERROR

LIMIT (SERL)

(Bits 2, 1 and 0)

This 3-bit number specifies the maximum number of bits that can be in error in the

synchronisation word. When the synchronisation word is recognised with less than

or equal to this number of errors the SYNCF bit is set to "1" and the actual number of

errors is loaded into SYNC ERRORS. The RXDATA is then loaded into the registers

for "Data Symbols 0 to 62", the Rx syndrome is updated, and an interrupt may be

generated, depending on the state of the IRQ MASK register. If 5, 6 or 7 errors are

programmed to be accepted in the SYNC ERROR LIMIT, falsing of the forward

channel sync word may occur.

IRQ MASK Register (Hex address $31)

These bits prevent interrupts from occurring as detailed below:

SYNCM

(Bit 7)

When this bit is set to "1" the SYNC interrupt will be gated out to the IRQN pin. When

this bit is set to "0" the SYNC interrupt will be inhibited. This bit has no effect on the

contents of the STATUS register.

DECM

(Bit 6)

When this bit is set to "1" the DEC interrupt will be gated out to the IRQN pin. When

this bit is set to "0" the DEC interrupt will be inhibited. This bit has no effect on the

contents of the STATUS register.

IDLEM

(Bit 5)

When this bit is set to "1" the IDLE interrupt will be gated out to the IRQN pin. When

this bit is set to "0" the IDLE interrupt will be inhibited. This bit has no effect on the

contents of the STATUS register.

TXM

(Bit 4)

When this bit is set to "1" the Tx interrupt will be gated out to the IRQN pin. When

this bit is set to "0" the Tx interrupt will be inhibited. This bit has no effect on the

contents of the STATUS register.

TIMERM

(Bit 3)

When this bit is set to "1" the TIMER interrupt will be gated out to the IRQN pin.

After this bit is set to "0" the TIMER interrupt will be inhibited. This bit has no effect

on the contents of the STATUS register.

ERRM

(Bit 2)

For systems that are required to work error free and where Reed-Solomon error

correction is not implemented, this bit provides the means not to interrupt the

controlling µP if errors are detected. When this bit is set to "1" all the interrupts will

work as specified. When this bit is set to "0", the SYNC, DEC and IDLE interrupts

will be inhibited even if the on chip Reed-Solomon error detector indicates there are

errors in the data, thus not wasting the controlling µP's time with interrupts for

incorrect data.