CDPD Wireless Modem Data Pump

FX949

© 1996 Consumer Microcircuits Limited

16

D/949/5

(7)

The data is EXORed with the pseudorandom sequence (PRBS) as it is transmitted. Once this

is done, the output buffer will be empty and the TXF flag with interrupt will be generated,

looping the control sequence back to the first step.

(8)

The input buffer can be re-loaded while the transmitter is transmitting.

(9)

The CI (continuity indicator) bit is automatically inserted every 9 symbols, during transmission.

(10)

The 38 bit "dotting sequence" and 22 bit block synchronisation word are added if it is the first

transmission after Tx powersave or if the CI bit has just previously gone from "0" to "1"

indicating the start of a new transmission block.

(11)

The signal generated has a data rate of 19.2k bits/sec and is filtered by a Gaussian filter with a

BT of 0.5 in the transmit section of the GMSK modem.

1.6.3

Receiver (forward channel)

(1)

The SYNC ERROR LIMIT (SERL) (Bits 2, 1 and 0 of the CONTROL register) is set from "0" to

"7" as required by the application.

(2)

The receiver is enabled using PSRX (Bit 5 of the CONTROL register).

(3)

The receiver is now able to receive 19.2k bits/sec data via the receive section of the GMSK

modem, comprising input filter, slicer and bit synchroniser.

(4)

A continuous stream of data is fed into the receiver input shift register.

(5)

When the controlling µP receives a carrier detect, it can pulse ACQ (Bit 7 of the CONTROL

register) in order to quickly acquire bit synchronisation. If carrier detect is not available or, due

to powersave requirements, the controlling device remains unpowered, then slower bit

synchronisation will be acquired in approximately 32 bits.

(6)

The receiver input shift register is continually monitored for the 35-bit synchronisation word

interleaved with the data. It correlates the number of errors in the synchronisation word with

the maximum number allowed (previously programmed into the SYNC ERROR LIMIT bits of

the CONTROL register).

When it achieves this limit or less, valid data is assumed to be

present.

(7)

The data is EXORed with the pseudorandom sequence (PRBS) and a 16-symbol syndrome is

generated. The data and syndrome are then loaded into the Rx output registers, ready for

reading by the controlling µP.

(8)

DEC (Bit 6) and IDLE (Bit 5) of the STATUS register are set according to the data received.

(9)

SYNCF (Bit 7 of the IRQ FLAGS register) is set and an IRQ is generated. SYNC (Bit 7 of the

STATUS register) is set to "1". This indicates that a new block of data has successfully been

received and is available for reading by the controlling µP.

(10)

With the first block sync received, the device now checks the DEC and IDLE positions in the

next block of data and outputs them with interrupts as they are counted in.