CDPD Wireless Modem Data Pump

FX949

© 1996 Consumer Microcircuits Limited

15

D/949/5

1.6

Application Notes

Further information on Reed-Solomon codes may be found in "Error Control Coding" by S. Lin and D.J.

Costello, published by Prentice Hall in 1983. The ISBN number is 0-13-283796-X.

The operation of the FX949 can be split into 3 sections: the Transmitter (reverse channel), the

Receiver (forward channel) and the Timer. The operational sequence of each is described below, with

reference to the internal block diagram, shown in Figure 4. Data and framing transmission structures

are shown in Figure 5 for the reverse channel and in Figure 6 for the forward channel.

1.6.1

General

(1)

After power up, enable or disable the interrupts by using the IRQ MASK register, depending on

whether the IRQN signal or direct polling of the IRQ FLAGS register is being used.

(2)

After power up, program PSRX (Bit 5 of the CONTROL register) to "1" to initialise the Rx

circuitry, i.e:

reset the interrupts

reset SYNCF, DECF, IDLEF in the IRQ FLAGS register

reset SYNC, DEC, IDLE, ERROR, SYNC ERRORS in the STATUS register

All other Rx registers are not affected and will be in a random state after power up.

(3)

After power up, program PSTX (Bit 4 of the CONTROL register) to "1" to initialise the Tx

circuitry, i.e:

set TXF in the IRQ register to "1" to indicate that the Tx buffer is empty

set the interrupt IRQN, if enabled, to request Tx data from the controlling µP

1.6.2

Transmitter (reverse channel)

(1)

After power up, a Tx interrupt is generated, if enabled, and TXF (Bit 4 of the IRQ FLAGS

register) is set, indicating the output buffer is empty.

(2)

The transmitter can now be enabled.

(3)

CI (Bit 3 of the CONTROL register) should be set to "1" when there are more Tx blocks to

follow and set to "0" for the last block. If there is only one block to be sent, i.e. the first block is

the last block, then the CI bit should be pulsed from "0" to "1" to "0" to ensure that the dotting

pattern and block sync are sent and that CI is set to "0" to indicate the presence of the last

block, except just after powersave when the dotting sequence and block sync are added

automatically.

(4)

All 47 symbols (0 to 46) are loaded into the TXDATA registers from the controlling µP, finishing

the load with the 47th symbol. This set of TXDATA registers is double buffered, therefore any

previous data can be sent again by re-loading only symbol 46, i.e. loading symbol 46 indicates

that data is ready to be sent.

(5)

The loading of symbol 46 (as above [4]) triggers the generation of a Reed-Solomon 16 symbol

parity code, based on symbols 0 to 46 in the input buffer.

(6)

The transmitter will wait for the output buffer to become empty (if it is the first transmission it

may already be empty). When this condition is met, data is transferred to the output buffer. At

this point the data and C1 bit for that block have been defined and will not change whilst setting

up for the next block to be sent.