CDPD Wireless Modem Data Pump

FX949

© 1996 Consumer Microcircuits Limited

17

D/949/5

(11)

On-chip circuitry predicts when the next block sync will arrive. If it arrives before that time, the

circuit is reset and the sequence loops back to step (6). If the time expires, the SYNCF and

IRQ signals will be generated and SYNC (Bit 7 of the STATUS register) will be set to "0",

indicating that block sync has been lost and DEC, IDLE and RXDATA are no longer valid.

1.6.4

Timer

(1)

The IRQ FLAGS register is read, to reset TIMEF (Bit 3).

(2)

The TIMER register is programmed with the time required, from 1 to 255 seconds, starting the

time-out.

(3)

IRQ and TIMEF are set when time expires.

(4)

This timer can be used to implement the "sleep mode", as described in the CDPD specification.