F71869 datasheet(91/116 Pages) FINTEK

91 / 116 page

Fintek

Feature Integration Technology Inc.

2009

V1.1

F71869

GPIO13_DET_SEL R/W

When GPIO13 is in input mode, set this bit to select which input event

should be detected.

0: rising edge

1: falling edge

GPIO12_DET_SEL R/W

When GPIO12 is in input mode, set this bit to select which input event

should be detected.

0: rising edge

1: falling edge

GPIO11_DET_SEL R/W

When GPIO11 is in input mode, set this bit to select which input event

should be detected.

0: rising edge

1: falling edge

GPIO10_DET_SEL R/W

When GPIO10 is in input mode, set this bit to select which input event

should be detected.

0: rising edge

1: falling edge

6.8.15 GPIO1 Event Status Register

⎯ Index E6h

Bit

Name

R/W Default

Description

GPIO17_

EVENT_STS

R/W

When GPIO17 is in input mode and a GPIO17 input is detected

according to CRE5[7], this bit will be set to 1. Write a 1 to this bit will

clear it to 0.

GPIO16_

EVENT_STS

R/W

When GPIO16 is in input mode and a GPIO16 input is detected

according to CRE5[6], this bit will be set to 1. Write a 1 to this bit will

clear it to 0.

GPIO15_

EVENT_STS

R/W

When GPIO15 is in input mode and a GPIO15 input is detected

according to CRE5[5], this bit will be set to 1. Write a 1 to this bit will

clear it to 0.

GPIO14_

EVENT_STS

R/W

When GPIO14 is in input mode and a GPIO14 input is detected

according to CRE5[4], this bit will be set to 1. Write a 1 to this bit will

clear it to 0.

GPIO13_

EVENT_STS

R/W

When GPIO13 is in input mode and a GPIO13 input is detected

according to CRE5[3], this bit will be set to 1. Write a 1 to this bit will

clear it to 0.

GPIO12_

EVENT_STS

R/W

When GPIO12 is in input mode and a GPIO12 input is detected

according to CRE5[2], this bit will be set to 1. Write a 1 to this bit will

clear it to 0.

GPIO11_

EVENT_STS

R/W

When GPIO11 is in input mode and a GPIO11 input is detected

according to CRE5[1], this bit will be set to 1. Write a 1 to this bit will

clear it to 0.

GPIO10_

EVENT_STS

R/W

When GPIO10 is in input mode and a GPIO10 input is detected

according to CRE5[0], this bit will be set to 1. Write a 1 to this bit will

clear it to 0.

6.8.16 GPIO2 Output Enable Register

⎯ Index D0h

Bit

Name

R/W Default

Description

F71869 Datasheet(PDF) 91 Page - Feature Integration Technology Inc.

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