AD9284 datasheet(14/24 Pages) AD

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AD9284

Rev. 0 | Page 14 of 24

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9284 sample clock inputs,

CLK+ and CLK− with a differential signal. The signal is typically

ac-coupled into the CLK+ and CLK− pins via a transformer or

capacitors.

Clock Input Options

The AD9284 has a very flexible clock input structure. The clock

input can be an LVDS, LVPECL, or sine wave signal. Each configu-

ration that is described in this section applies to CLK+ and CLK−.

Figure 21 and Figure 22 show the two preferred methods for

clocking the AD9284. A low jitter clock source is converted

from a single-ended signal to a differential signal using either

an RF transformer or an RF balun. The back-to-back Schottky

diodes across the transformer/balun secondary limit clock

excursions into the AD9284 to approximately 0.8 V p-p

differential.

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9284, while

preserving the fast rise and fall times of the signal that are

critical to low jitter performance.

0.1µF

SCHOTTKY

DIODES:

HSM2822

50Ω 100Ω

CLK–

CLK+

ADC

Mini-Circuits®

ADT1-1WT, 1:1 Z

XFMR

CLOCK

INPUT

Figure 21. Transformer-Coupled Differential Clock

0.1µF

SCHOTTKY

DIODES:

HSM2822

1nF

50Ω

CLK–

CLK+

ADC

CLOCK

INPUT

Figure 22. Balun-Coupled Differential Clock

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 23. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer

excellent jitter performance.

100Ω

0.1µF

240Ω

50kΩ

CLK–

CLK+

ADC

AD951x

PECL DRIVER

CLOCK

INPUT

CLOCK

INPUT

Figure 23. Differential PECL Sample Clock

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 24. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517

clock drivers offer excellent jitter performance.

100Ω

0.1µF

50kΩ

CLK–

CLK+

ADC

AD951x

LVDS DRIVER

CLOCK

INPUT

CLOCK

INPUT

Figure 24. Differential LVDS Sample Clock

DIGITAL OUTPUTS

Digital Output Enable Function (OE)

The AD9284 has a flexible three-state ability for the digital output

pins. The three-state mode is enabled using the OE pin. When

OE is set to logic level high, the output drivers for both data buses

are placed into a high impedance state.

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