AD6641

Rev. 0 | Page 12 of 28

Pin No.

Mnemonic

Description

40

CML

Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized

internal bias voltage for VIN+ and VIN−.

44

CLK+

Clock Input—True.

45

CLK−

Clock Input—Complement.

49

FILL+

FIFO Fill Input (LVDS)—True.

50

FILL−

FIFO Fill Input (LVDS)—Complement.

51

FULL

FIFO Full Output Indicator.

52

EMPTY

FIFO Empty Output Indicator.

53

DUMP

FIFO Readback Input.

55

PCLK−

Data Clock Output—Complement.

56

PCLK+

Data Clock Output—True.