AD6641

Rev. 0 | Page 13 of 28

PD0

VIN+

VIN–

AVDD

AVDD

AVDD

CML

AVDD

AVDD

AVDD

AVDD

AVDD

VREF

AVDD

SPI_VDDIO

DNC

DNC

PD1

PD2

PD3

DRVDD

DRGND

PD4

PD5

PD6

PD7

PD8

PD9

PIN 1

INDICATOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

35

36

37

38

39

40

41

42

34

33

32

31

30

29

AD6641

TOP VIEW

(Not to Scale)

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD IS THE ONLY ANALOG GROUND

CONNECTION FOR THE CHIP. IT MUST BE CONNECTED TO PCB AGND.

Figure 9. Pin Configuration for Parallel CMOS Mode

Table 9. Parallel CMOS Mode Pin Function Descriptions

Pin No.

Mnemonic

Description

0

EPAD

Exposed Pad. The exposed pad is the only ground connection for the chip. The pad must be

connected to PCB AGND.

1, 2, 18, 19, 20, 28, 54

DNC

Do Not Connect. Do not connect to this pin.

3

PD0

PD0 Data Output.

4

PD1

PD1 Data Output.

5

PD2

PD2 Data Output.

6

PD3

PD3 Data Output.

7, 24, 47

DRVDD

1.9 V Digital Output Supply.

8, 23, 48

DRGND

Digital Output Ground.

9

PD4

PD4 Data Output.

10

PD5

PD5 Data Output.

11

PD6

PD6 Data Output.

12

PD7

PD7 Data Output.

13

PD8

PD8 Data Output.

14

PD9

PD9 Data Output.

15

PD10

PD10 Data Output.

16

PD11

PD11 Data Output (MSB).

17

SP_SDO

SPORT Output.

21

SP_SDFS

SPORT Frame Sync Input (Slave Mode)/Output (Master Mode).

22

SP_SCLK

SPORT Clock Input (Slave Mode)/Output (Master Mode).

25

SDIO

Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).

26

SCLK

Serial Port Interface Clock (Serial Port Mode).

27

CSB

Serial Port Chip Select (Active Low).

29

SPI_VDDIO

1.9 V or 3.3 V SPI I/O Supply.

30, 32, 33, 34, 37, 38, 39,

41, 42, 43, 46

AVDD

1.9 V Analog Supply.

31

VREF

Voltage Reference Input/Output. Nominally 0.75 V.

35

VIN+

Analog Input—True.

36

VIN−

Analog Input—Complement.

40

CML

Common-Mode Output. Enabled through the SPI, this pin provides a reference for the

optimized internal bias voltage for VIN+ and VIN−.

44

CLK+

Clock Input—True.