AD6641 datasheet(21/28 Pages) AD

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AD6641

Rev. 0 | Page 21 of 28

Addr.

(Hex)

Parameter Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default

Notes/

Comments

0x15

OUTPUT_ADJUST

[7:4] = 0000

LVDS

course

adjust:

0 =

3.5 mA

(default)

1 =

2.0 mA

LVDS fine adjust:

001 = 3.50 mA

010 = 3.25 mA

011 = 3.00 mA

100 = 2.75 mA

101 = 2.50 mA

110 = 2.25 mA

111 = 2.00 mA

0x00

0x16

OUTPUT_PHASE

Output

clock

polarity:

1 =

inverted

0 =

normal

(default)

[6:0] = 0000000

0x03

0x17

OUTPUT_DELAY

Output clock delay:

0000 = 0

0001 = −1/10

0010 = −2/10

0011 = −3/10

0100 = reserved

0101 = +5/10

0110 = +4/10

0111 = +3/10

1000 = +2/10

1001 = +1/10

Shown as

fractional

value of

sampling

clock period

that is

subtracted or

added to

initial tSKEW,

see

Figure 3).

0x18

Input range

VREF select:

00 = internal VREF

(20 kΩ pull-down)

01 = import VREF

(0.59 V to 0.80 V on

VREF pin)

10 = export VREF

11= not used

Input voltage range setting (V):

11100 = 1.60

11101 = 1.58

11110 = 1.55

11111 = 1.52

00000 = 1.50

00001 = 1.47

00010 = 1.44

00011 = 1.42

00100 = 1.39

00101 = 1.36

00110 = 1.34

00111 = 1.31

01000 = 1.28

01001 = 1.26

01010 = 1.23

01011= 1.20

01100 = 1.18

0x19

USER_PATT1_LSB

[7:0]

User Defined

Pattern 1 LSB.

0x1A

USER_PATT1_MSB

[7:0]

User Defined

Pattern 1 MSB.

0x1B

USER_PATT2_LSB

[7:0]

User Defined

Pattern 2 LSB.

0x1C

USER_PATT2_MSB

[7:0]

User Defined

Pattern 2 MSB.

Digital Controls

0x101

Fill control register

Reserved

Fill

input

disable

Reserved

LIFO

mode

FIFO fill mode:

00 = single

01 = continuous

1x = reserved

Reserved

Standby

after fill

0x102

FIFO Config

[7:4] = reserved

Dump

reset

Fill reset

Dump

Fill

0x104

Fill count

[7:0]

0x7F

Number of

words to use

for fill or

dump.

AD6641 Datasheet(PDF) 21 Page - Analog Devices

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