AD6649EBZ datasheet(36/40 Pages) AD

36 / 40 page

AD6649

Rev. 0 | Page 36 of 40

MEMORY MAP REGISTER DESCRIPTION

For more information on functions controlled in Register 0x00

to Register 0x25, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

Sync Control (Register 0x3A)

Bits[7:3]—Reserved

Bit 2—Clock Divider Next Sync Only

If the master sync buffer enable bit (Address 0x3A, Bit 0) and

the clock divider sync enable bit (Address 0x3A, Bit 1) are high,

Bit 2 allows the clock divider to sync to the first sync pulse that it

receives and to ignore the rest. The clock divider sync enable bit

(Address 0x3A, Bit 1) resets after it syncs.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 is high and Bit 0 is high. This is continuous

sync mode.

Bit 0—Master Sync Buffer Enable

Bit 0 must be set high to enable any of the sync functions. If

the sync capability is not used, this bit should remain low to

conserve power.

DC Correction Control (Register 0x40)

Bit 7—Reserved

Bit 6—DC Correction Freeze

When Bit 6 is set high, the dc correction is no longer updated to

the signal monitor block, which holds the last dc value calculated.

Bits[5:2]—DC Correction Bandwidth Select

Bits[5:2] set the averaging time of the signal monitor dc

correction function. This 4-bit word sets the bandwidth of the

correction block, according to the following equation:

−

CLK

Corr

where:

k is the 4-bit value programmed in Bits[5:2] of Register 0x40

(values between 0 and 13 are valid for k; programming 14 or 15

provides the same result as programming 13).

fCLK is the AD6649 ADC sample rate in hertz.

Bit 1—DC Correction Enable

Setting this bit high causes the output of the dc measurement

block to be summed with the data in the signal path to remove

the dc offset from the signal path.

Bit 0—Reserved

Fast Detect Control (Register 0x45)

Bits[7:4]—Reserved

Bit 3—Force FD Output Enable

Setting this bit high forces the FD output pin to the value

written to Bit 2 of this register (Register 0x45). This enables the

user to force a known value on the FD pin for debugging.

Bit 2—Force FD Output Value

The value written to Bit 2 is forced on the FD output pin when

Bit 3 is written high.

Bit 1—Reserved

Bit 0—Enable Fast Detect Output

Setting this bit high enables the output of the upper threshold

FD comparator to drive the FD output pin.

Fast Detect Upper Threshold

(Register 0x47 and Register 0x48)

These registers provide an upper limit threshold. The 13-bit

value is compared with the output magnitude from the ADC

block. If the ADC magnitude exceeds this threshold value, the

FD output pin is set if Bit 0 in Register 0x45 is set.

Fast Detect Lower Threshold

(Register 0x49 and Register 0x4A)

These registers provide a lower limit threshold. The 13-bit value

is compared with the output magnitude from the ADC block. If

the ADC magnitude is less than this threshold value for the

number of cycles programmed in the dwell time register, the FD

output bit is cleared.

Fast Detect Dwell Time

(Register 0x4B and Register 0x4C)

These register values set the minimum time in ADC sample

clock cycles (after clock divider) that a signal needs to stay below

the lower threshold limit before the FD output bits are cleared.

Filter Control (Register 0x50)

Bit 7—Reserved (Reads Back as 1)

Bit 6—Reserved

Bit 5—Reserved (Reads Back as 1)

Bit 4—FIR Mode

Setting this bit low enables the high performance FIR filter.

Setting this bit high enables the low latency FIR.

Bit 3—Output Gain

Setting this bit high sets the output gain to −6 dB. A 0 value on

this bit sets the gain at 0 dB.

AD6649EBZ Datasheet(PDF) 36 Page - Analog Devices

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