AD6649EBZ datasheet(24/40 Pages) AD

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AD6649

Rev. 0 | Page 24 of 40

FIR FILTERS

The two FIR filters that can be used are either a 47-tap, high

performance, fixed-coefficient FIR filter or a 21-tap, low latency,

fixed-coefficient FIR filter. These filters are useful in providing

alias protection at the device output. The high performance FIR

is a simple sum-of-products FIR filter with 47 filter taps and

21-bit fixed coefficients. Note that this filter does not decimate.

The normalized coefficients used in the implementation and the

decimal equivalent value of the coefficients are listed in Table 12.

Table 12. High Performance FIR Filter Coefficients

Coefficient

Number

Normalized

Coefficient

Decimal Coefficient

(21-Bit)

C0, C46

−0.0001335

−140

C1, C45

−0.0009689

−1016

C2, C44

−0.0024185

−2536

C3, C43

−0.0019341

−2028

C4, C42

0.0023584

2473

C5, C41

0.0051260

5375

C6, C40

−0.0009680

−1015

C7, C39

−0.0086231

−9042

C8, C38

−0.0011368

−1192

C9, C37

0.0142097

14900

C10, C36

0.0064697

6784

C11, C35

−0.0207596

−21768

C12, C34

−0.0161047

−16887

C13, C33

0.0274601

28794

C14, C32

0.0310631

32572

C15, C31

−0.0348339

−36526

C16, C30

−0.0557785

−58488

C17, C29

0.0415993

43620

C18, C28

0.0986786

103472

C19, C27

−0.0463982

−48652

C20, C26

−0.1893501

−198548

C21, C25

0.0505829

53040

C22, C24

0.6113434

641040

C23

0.9171314

961682

FIR SYNCHRONIZATION

The AD6649 filters within a single part or across multiple parts can

be synchronized using the external SYNC input. The filters can

be configured to be resynchronized on every SYNC signal or only

on the first SYNC signal after the SPI control register is written.

A valid SYNC causes the FIR filter to restart at the programmed

decimation phase value. Bit 4 and Bit 5 of Register 0x58 allow

the FIR to be resynchronized on every SYNC signal or only on

the first SYNC signal after the register is written.

FILTER PERFORMANCE

When using the fixed-frequency NCO and a 95 MHz FIR filter,

the output rate is equal to the sample clock rate. The composite

response of this mode is shown in Figure 41. The detailed pass-

band response for this mode is shown in Figure 42. To place the

part in this mode, set SPI Register 0x50 to 0xB0. When operating

in this mode, the NCO must be placed at fS/4, and the low latency

NCO select bit (Bit 0) in Register 0x5A must be set. It is important

to note that a −1.0 dBFS input level at the analog inputs corresponds

to an output level of −2.5 dBFS when using the low latency FIR

filter. This output level reduction is a result of the −1.5 dB pass-

band attenuation in the FIR filter in this mode and does not

result in loss in the dynamic range of the converter.

–1

–2

–3

–4

30.72

61.44

92.16

122.88

FILTER RESPONSE (MHz)

Figure 41. Low Latency FIR Filter Composite Response at 245.76 MSPS

(Fixed-Frequency NCO, 95 MHz FIR Filter Mode)

–1.000

–1.125

–1.250

–1.375

–1.500

30.72

61.44

92.16

122.88

FILTER RESPONSE (MHz)

Figure 42. Low Latency FIR Filter Pass-Band Response at 245.76 MSPS

(Fixed-Frequency NCO, 95 MHz FIR Filter Mode)

When using the tunable-frequency NCO and 100 MHz FIR filter,

the output rate is equal to the sample clock rate. The response of

the high performance FIR filter is shown in Figure 43. The detailed

pass-band response for this mode is shown in Figure 44. To place

the part into this mode, set SPI Register 0x50 to 0xA0. When

using the high performance FIR filter, the output level is −1.3 dBFS

for a corresponding input level of −1.0 dBFS at the analog inputs.

This is a result of the −0.3 dB pass-band attenuation of the FIR

filter in this mode and does not result in loss in the dynamic range

of the converter.

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