AD6649EBZ datasheet(37/40 Pages) AD

37 / 40 page

AD6649

Rev. 0 | Page 37 of 40

Bit 2—9-bit Output Mode Enable

If this bit is set, the NCOs and filters are bypassed and the part

outputs nine bits of data. These nine bits are presented on the

nine MSBs of the output bus (that is, Bit D13 through Bit D5).

Bits[1:0]—Datapath Gain

These bits set the datapath gain as follows:

00 = 0 dB gain

01 = −6 dB gain

10 = −12 dB gain

11 = −18 dB gain

NCO Control (Register 0x51)

Bit 7—Reserved

Bit 6—NCO32 to fS/4 NCO Sync Enable

This bit should be set high when NCO32 is set to fS/4 using the

fixed-frequency NCO and the 95 MHz FIR filter. It should be

disabled when using the tunable-frequency NCO and 100 MHz

FIR filter.

Bit 5—Spectral Reversal

This bit should be set high to reverse the output frequency

spectrum.

Bit 4—Reserved (Reads Back as 1)

Bit 3—Reserved

Bit 2—NCO32 Amplitude Dither Enable

When Bit 2 is set, amplitude dither in the NCO is enabled.

When Bit 2 is cleared, amplitude dither is disabled.

Bit 1—NCO32 Phase Dither Enable

When Bit 2 is set, phase dither in the NCO is enabled. When

Bit 2 is cleared, phase dither is disabled.

Bit 0—Reserved (Reads Back as 1)

NCO Frequency (Register 0x52 to Register 0x55)

This 32-bit value is used to program the NCO tuning frequency.

The frequency value to be programmed is given by the

following equation:

CLK

Mod

NCO_FREQ

)

(

where:

NCO_FREQ is a 32-bit twos complement number representing

the NCO frequency register.

f is the desired carrier frequency in hertz.

fCLK is the AD6649 ADC clock rate in hertz.

NCO Phase Offset (Register 0x56 and Register 0x57)

The 16-bit value programmed into the NCO phase value register

is loaded into the NCO block each time the NCO is started or

when an NCO SYNC signal is received. This process allows the

NCO to be started with a known nonzero phase.

Use the following equation to calculate the NCO phase offset value:

NCO_PHASE = 216 × PHASE/360

where NCO_PHASE is a decimal number equal to the 16-bit binary

number to be programmed at Register 0x56 and Register 0x57,

and PHASE is the desired NCO phase in degrees.

SYNC Control (Register 0x58)

Bit 7—fS/4 NCO Next Sync Only

If the master sync buffer enable bit (Register 0x3A, Bit 0) and

the fS/4 NCO sync enable bit (Register 0x58, Bit 6) are high, Bit 7

allows the fS/4 NCO to synchronize following the first sync

pulse that it receives and ignore the rest. If Bit 7 is set, Bit 6 of

Bit 6—fS/4 NCO Sync Enable

Bit 6 gates the sync pulse to the fS/4 NCO. When Bit 6 is set

high, the sync signal causes the fS/4 NCO to synchronize.

This sync is active only when the master sync buffer enable bit

(Register 0x3A, Bit 0) is high. This is continuous sync mode.

Bit 5—FIR Next Sync Only

If the master sync buffer enable bit (Register 0x3A, Bit 0) and the

FIR sync enable bit (Register 0x58, Bit 4) are high, Bit 5 allows

the FIR to synchronize following the first sync pulse that it receives

and to ignore the rest. If Bit 5 is set, Bit 4 of Register 0x3A resets

after this sync occurs.

Bit 4—FIR Sync Enable

Bit 4 gates the sync pulse to the FIR filter. When Bit 4 is set

high, the sync signal causes the half-band to resynchronize.

This sync is active only when the master sync buffer enable bit

(Register 0x3A, Bit 0) is high. This is continuous sync mode.

Bits[3:2]—Reserved

Bit 1—NCO32 Next Sync Only

If the master sync buffer enable bit (Register 0x3A, Bit 0) and

the NCO32 sync enable bit (Register 0x58, Bit 0) are high, Bit 1

allows the NCO32 to synchronize following the first sync pulse

that it receives and to ignore the rest. Bit 0 of Register 0x58 resets

after a sync occurs if Bit 1 is set.

Bit 0—NCO32 Sync Enable

Bit 0 gates the sync pulse to the 32-bit NCO. When this bit is set

high, the sync signal causes the NCO to resynchronize, starting

at the NCO phase offset value. This sync is active only when the

master sync buffer enable bit (Register 0x3A, Bit 0) is high. This

is continuous sync mode.

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