Whilst a device is responding to a request for remote loopback

from the far-end, requests from the near-end to initiate remote

loopbacks will be ignored.

Drift Lock

Communicating modems attain a stable state where the ‘transmit’

window of one modem coincides with the ‘receive’ window of the

other, allowing for delay through the optical link. Adjustments to

machine cycles are made automatically during operation, to

compensate for differences in XTAL frequencies which would

otherwise cause loss of synchronisation.

Drift lock synchronisation described above, depends on a

difference in the XTALfrequencies at each end of the link, and the

greater the difference the faster the locking. Therefore, if the

difference between XTAL frequencies is very small (a few ppm),

automatic locking may take tens of seconds or even minutes.

Drift lock will not operate if the two communicating devices are

driven by a clock derived from a single source (i.e. tolerance of 0

ppm).

Active Lock

Active lock mode may be used to accelerate synchronisation of a

pair of communicating modems. This mode synchronises the

modems with less than 3.0 seconds delay, by adjusting the

machine cycles of the modems. Active lock reduces the machine

cycle of the device by 0.3 % ensuring rapid lock.

After

synchronisation the machine cycle reverts automatically to

normal.

Note that only one device can be configured in active lock mode

at any one time, and thus the DM(1:3) pins must not be

permanently wired High on both devices in a production system.

Active lock mode is usually invoked temporarily on power-up.

This can be achieved on the ACS401 by connecting DM1, DM2

and DM3 together, and attaching that node to an RC arrangement

with the capacitor to 5 V and the resistor to GND, to create a 5 V

  0 V ramp on power-up. The RC time constant should be > 5

seconds.

Active lock will succeed even when communicating devices are

driven from clocks derived from a single source (i.e. 0 ppm).

Random Lock

This mode achieves moderate locking times (typically 4 seconds,

worst case 12 seconds) with the advantage that the ACS401’s are

configured as peers.

Communicating modems may be

permanently configured in this mode (i.e. with hard-wired DM(1:3)

pins).

Random lock operates even when communicating devices are

driven from clocks derived from a single source. Random lock

mode is compatible with drift lock and active lock.

Memory Lock

Following the assertion of a reset (PORB = 0) communicating

devices will initiate an arbitration process where within 12 seconds

the communicating modems will achieve synchronisation. One

establishing itself as an active lock modem and the other

establishing itself as a drift lock modem. On subsequent attempts

to lock, typically where the fiber has been disconnected and a new

fiber inserted, synchronisation will be achieved within 3 seconds.

It is only necessary to apply PORB to one device in the

communicating pair to initiate an arbitration process.

Since memory lock status (active or drift) uses on-chip storage,

loss of power to the IC will require a new reset (PORB = 0).

Furthermore, should there be a need to synchronise with a third

modem, reset will again be required.

Mixing Lock modes

It is possible to mix all combinations of locking modes once the

modems are locked, however, prior to synchronisation two

modems configured in active lock will not operate. The effect of

mixing locking modes on locking speed is tabulated below:

Device A

Device B

Locking Speed

Mode

Mode

Drift

Drift

Drift

Drift

Active

Active

Drift

Random

Random

Drift

Memory

Random

Active

Active

Not allowed

Active

Random

Random

Active

Memory

Random

Random

Random

Random

Random

Memory

Random

Memory

Memory

Active*

* Memory lock has random lock speed for the first synchronisation

HBT Status pin (‘Heartbeat’ Indicator LED)

The ACS401 HBTpin affords a method of driving a display LED in

a manner which is sympathetic to low power consumption. The

HBT pin is pulsed to indicate ‘locked’status (DCDB = 0) and ‘out

of lock’ status (DCDB = 1). The frequency of pulses is 16 times

greater for ‘out of lock’ than for ‘lock’. The LED ‘on’ indicates

power-up whilst the frequency of pulsing denotes locking status.

Since the display LED is on for at most 6.4 % of the total time, the

HBT requires little power which may be further reduced by

employing high efficiency LEDs. The formulas below presume

‘standard’ mode of operation; for ‘double’ mode the XTAL value

should be divided by 2.

Powered-up, but not locked

Frequency (Hz):

Duration (s):

73,728 / XTAL

On time (%):

6.4 % of time.

With 9.216 MHz XTAL and ‘standard’ mode

Frequency:

8 Hz (approx.)

Duration :

8 ms (approx.)

Powered-up and locked

Frequency (Hz):

XTAL/ 18,432

Duration (s):

73,728 / XTAL

On time (%):

0.4 % of time.

With 9.216 MHz XTAL and ‘standard’ mode

Frequency:

0.5 Hz (approx.)

Duration :

8 ms (approx.)

The HBT pin is active High and can supply up to 16 mA at a

voltage of > VDD - 0.5 Volts. The display LED should be placed

between the HBTpin and GND with a series resistor. The resistor

value is a function of the efficiency of the display LED, and the

power budget.

Example: Calculating the HBT resistor value

LED on voltage:

2.0 V

VDD (ACS401):

5.0 V

Resistor voltage:

3.0 V

Current to LED:

2 mA (high efficiency LED)

Resistor value:

3 / 2 * 10-3 = 1500

Ω

Note: The LED referred to in this section is of the inexpensive

display type and should not be confused with the LED that

interfaces with the fiber optic cable itself.

ERC and ERL (Error Detector)

These signals can be used to give an indication of the quality of

the optical link. Even when a DC signal is applied to the data,

handshake and TxCL inputs, the ACS401 modem transmits

approximately 40 kbps over the link in each direction. This control

data is used to maintain the timing and the relative positioning of

‘transmit’and ‘receive’ windows.

The transmit and control data is constantly monitored to make

sure it is compatible with the 3B4B format. If a coding error is

detected than ERL will go High and will remain High until reset.

ERL may be reset by asserting PORB or by removing the fiber-

optic cable from one side of the link thereby forcing the device

temporarily out of lock.