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EM773 Datasheet(PDF) 32 Page - NXP Semiconductors |
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EM773 Datasheet(HTML) 32 Page - NXP Semiconductors |
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32 / 45 page ![]() EM773 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Objective data sheet Rev. 1 — 1 September 2010 32 of 45 NXP Semiconductors EM773 Energy metering IC 10.4 I/O pins [1] Applies to standard port pins and RESET pin. 10.5 I2C-bus [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. Table 10. Dynamic characteristic: I/O pins[1] Tamb = −40 °C to +85 °C; 3.0 V ≤ VDD ≤ 3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns Table 11. Dynamic characteristic: I2C-bus pins[1] Tamb = −40 °C to +85 °C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz tf fall time [4][5][6][7] of both SDA and SCL signals Standard-mode -300 ns Fast-mode 20 + 0.1 × C b 300 ns Fast-mode Plus - 120 ns tLOW LOW period of the SCL clock Standard-mode 4.7 - μs Fast-mode 1.3 - μs Fast-mode Plus 0.5 - μs tHIGH HIGH period of the SCL clock Standard-mode 4.0 - μs Fast-mode 0.6 - μs Fast-mode Plus 0.26 - μs tHD;DAT data hold time [3][4][8] Standard-mode 0 - μs Fast-mode 0 - μs Fast-mode Plus 0 - μs tSU;DAT data set-up time [9][10] Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns |
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