EM773 datasheet(12/45 Pages) NXP

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EM773

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Objective data sheet

Rev. 1 — 1 September 2010

12 of 45

NXP Semiconductors

EM773

Energy metering IC

7.10.1 Features

• The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The

I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus can be used for test and diagnostic purposes.

• The I2C-bus controller supports multiple address recognition and a bus monitor mode.

7.11 Metrology engine

The EM773 contains a metrology engine designed to collect voltage and current inputs to

calculate the active power, reactive power, apparent power and power factor of a load.

The purpose of the metrology engine is for non-billing applications such as plug meters,

smart appliances, industrial and consumer sub-meters, etc.

7.11.1 Features

• 1 % accurate for scalable input sources up to 230 V/50 Hz/16 A and

110 V/60 Hz/20 A while maintaining this accuracy with a factor of 1 to 400 down from

this maximum current.

• Automatically calculates active power in W, reactive power in VAr, apparent power in

VA, power factor ratio, Vrms and Irms without ARM CPU intervention.

• Standard API for initializing, starting, stopping and reading data from the metrology

engine using the ARM Cortex M0.

7.12 General purpose external event counter/timers

The EM773 includes two 32-bit counter/timers and one 16-bit counter/timers. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes one capture input to trap the timer value

when an input signal transitions, optionally generating an interrupt.

7.12.1 Features

• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

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