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PCF8523 Datasheet(PDF) 31 Page - NXP Semiconductors |
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PCF8523 Datasheet(HTML) 31 Page - NXP Semiconductors |
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31 / 66 page  PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 30 March 2011 31 of 66 NXP Semiconductors PCF8523 Real-Time Clock (RTC) and calendar A programmable square wave is available at pin INT1/CLKOUT and pin CLKOUT, which are both open-drain outputs. Pin INT1/CLKOUT has both functions of INT1 and CLKOUT combined. The duty cycle of the selected clock is not controlled but due to the nature of the clock generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50. The STOP bit function can also affect the CLKOUT signal, depending on the selected frequency. When STOP is active, the INT1/CLKOUT and CLKOUT pins will be high-impedance for all frequencies except of 32.768 kHz, 16.384 kHz and 8.192 kHz. For more details, see Section 8.10. [1] Duty cycle definition: % HIGH-level time : % LOW-level time. [2] Default value. [3] Clock frequencies may be affected by offset correction. 8.9.1.2 Register Tmr_A_freq_ctrl [1] Default value. Table 33. CLKOUT frequency selection COF[2:0] CLKOUT frequency (Hz) Typical duty cycle[1] Effect of STOP bit 000[2] 32768 60 : 40 to 40 : 60 no effect 001 16384 50 : 50 no effect 010 8192 50 : 50 no effect 011 4096 50 : 50 CLKOUT = high-Z 100 1024 50 : 50 CLKOUT = high-Z 101 32 50 : 50[3] CLKOUT = high-Z 110 1 50 : 50[3] CLKOUT = high-Z 111 CLKOUT disabled (high-Z) Table 34. Tmr_A_freq_ctrl - timer A frequency control register (address 10h) bit description Bit Symbol Value Description 7 to 3 - - unused 2 to 0 TAQ[2:0] source clock for timer A (see Table 38) 000 4.096 kHz 001 64 Hz 010 1 Hz 011 1 60 Hz 111[1] 110 100 1 3600 Hz |
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