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PCF8523 Datasheet(PDF) 51 Page - NXP Semiconductors |
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PCF8523 Datasheet(HTML) 51 Page - NXP Semiconductors |
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51 / 66 page ![]() PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 30 March 2011 51 of 66 NXP Semiconductors PCF8523 Real-Time Clock (RTC) and calendar 13. Application information Fig 34. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 % SCL SDA tHD;STA tSU;DAT tHD;DAT tf tBUF tSU;STA tLOW tHIGH tVD;ACK 013aaa417 tSU;STO protocol START condition (S) bit 7 MSB (A7) bit 6 (A6) bit 0 (R/W) acknowledge (A) STOP condition (P) 1/fSCL tr tVD;DAT R1 and C1 are recommended to limit the Slew Rate (SR, see Table 46) of VDD. If VDD drops to fast, the internal supply switch to the battery is not guaranteed. Fig 35. Application diagram 013aaa341 PCF8523 OSCI OSCO INT1/ CLKOUT SCL SDA VDD VSS MASTER TRANSMITTER RECEIVER SCL SDA VDD VSS VBAT CLKOUT INT2 VDD RR R: pull-up resistor R = Cb R1 C1 tr |
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