PCF8523 datasheet(56/66 Pages) NXP

56 / 66 page

PCF8523

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Product data sheet

Rev. 3 — 30 March 2011

56 of 66

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

[1]

The x/y coordinates of the alignment mark location represent the position of the REF point (see Figure 40)

with respect to the center (x/y = 0) of the chip; see Figure 39.

[2]

The x/y values of the dimensions represent the extensions of the alignment mark in direction of the

coordinate axis (see Figure 40).

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

Table 49.

Bump locations

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 39.

Symbol

Bump

Coordinates (

m)

VDD

714.4

911.7

OSCI

714.4

988.3

OSCO

714.4

707.3

VBAT

714.4

199.3

VSS

714.4

459.1

n.c.

714.4

616.7

INT2

714.4

895.4

CLKOUT

714.4

922.0

SDA

714.4

528.8

SCL

714.4

101.1

n.c.

714.4

607.6

INT1/CLKOUT

714.4

763.2

Table 50.

Alignment mark dimension and location

Coordinates

Location[1]

631.3

m

891.7

m

Dimension[2]

44.25

m

36.5

m

Fig 40. Alignment mark

013aaa318

REF

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