PCF8523 datasheet(49/66 Pages) NXP

49 / 66 page

PCF8523

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 30 March 2011

49 of 66

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

[1]

For reliable oscillator start at power-up: VDD =VDD(min) +0.3 V.

[2]

For reliable oscillator start at power-up: VDD =VDD(min) +0.5 V.

[3]

Timer source clock = 1



3600 Hz, level of pins SCL and SDA is VDD or VSS.

[4]

In case of an ESD event, the value may increase slightly.

[5]

Implicit by design.

[6]

Tested on sample basis.

[7]

Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series:

[8]

Tested at 25

C.

[9]

Crystal characteristic specification.

Outputs

output voltage

on pins INT1/CLKOUT, CLKOUT, INT2,

SDA (refers to external pull-up voltage)

0.5

5.5

VOL

LOW-level output

voltage

VSS

-0.4

IOL

LOW-level output

current

output sink current;

on pins INT1/CLKOUT, CLKOUT, INT2;

VOL =0.4 V; VDD =5V

[6] 1.5

on pin SDA

VOL =0.4 V; VDD =3.0 V

[6] 20

ILO

output leakage current

VO =VSS or VDD

[4] -0

-nA

CL(itg)

integrated load

capacitance

on pins OSCO, OSCI

[7][8]

CL = 7 pF

3.3

CL = 12.5 pF

12.5

series resistance

[9] -

100



Table 46.

Static characteristics …continued

VDD = 1.2 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs =40 k; CL = 7 pF; unless otherwise

specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Litg



OSCI

OSCO





OSCI

OSCO



--------------------------------------------

PCF8523 Datasheet(PDF) 49 Page - NXP Semiconductors

PCF8523 Datasheet(HTML) 49 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL