PCF8523 datasheet(8/66 Pages) NXP

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PCF8523

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Product data sheet

Rev. 3 — 30 March 2011

8 of 66

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

8.2 Control and status registers

8.2.1 Register Control_1

[1]

Default value.

[2]

Must always be written with logic 0.

[3]

For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 8.3). Bit SR will

always return 0 when read.

CLOCKOUT and timer registers

0Fh

Tmr_CLKOUT_ctrl

TAM

TBM

COF[2:0]

TAC[1:0]

TBC

10h

Tmr_A_freq_ctrl

TAQ[2:0]

11h

Tmr_A_reg

TIMER_A_VALUE[7:0]

12h

Tmr_B_freq_ctrl

TBW[2:0]

TBQ[2:0]

13h

Tmr_B_reg

TIMER_B_VALUE[7:0]

Table 4.

Registers overview …continued

Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0.

Address Register name

Bit

Table 5.

Control_1 - control and status register 1 (address 00h) bit description

Bit

Symbol

Value

Description

CAP_SEL

internal oscillator capacitor selection for quartz

crystals with a corresponding load capacitance

0[1]

7pF

112.5 pF

0[1][2]

unused

5STOP

0[1]

RTC time circuits running

RTC time circuits frozen;

RTC divider chain flip-flops are

asynchronously set logic 0;

CLKOUT at 32.768 kHz, 16.384 kHz, or

8.192 kHz is still available

4SR

0[1][3]

no software reset

initiate software reset

12_24

0[1]

24 hour mode is selected

12 hour mode is selected

2SIE

0[1]

second interrupt disabled

second interrupt enabled

1AIE

0[1]

alarm interrupt disabled

alarm interrupt enabled

0CIE

0[1]

no correction interrupt generated

interrupt pulses will be generated at every

correction cycle (see Section 8.8)

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