TMS320F2812 datasheet(141/170 Pages) TI

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XCLKOUT

(1/2 XTIMCLK)

XHOLD

XR/

XZCS0AND1

XZCS2

XZCS6AND7

XD[15:0]

Valid

XHOLDA

d(HL-HiZ)

d(HH-HAH)

High-Impedance

XA[18:0]

Valid

d(HH-BV)

d(HL-HAL)

See Note (A)

See Note (B)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S – APRIL 2001 – REVISED MARCH 2011

Table 6-43. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)(1)(2)(3)

MIN

MAX

UNIT

td(HL-HiZ)

Delay time, XHOLD low to Hi-Z on all Address, Data, and Control

4tc(XTIM) + tc(XCO)

td(HL-HAL)

Delay time, XHOLD low to XHOLDA low

4tc(XTIM) + 2tc(XCO)

td(HH-HAH)

Delay time, XHOLD high to XHOLDA high

4tc(XTIM)

td(HH-BV)

Delay time, XHOLD high to Bus valid

6tc(XTIM)

(1)

When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance

state.

(2)

The state of XHOLD is latched on the rising edge of XTIMCLK.

(3)

After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of

XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the

maximum value specified.

All pending XINTF accesses are completed.

Normal XINTF operation resumes.

Figure 6-38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)

Electrical Specifications

141

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