LR38603 datasheet(13/26 Pages) SHARP

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LR38603

ADDRESS

NAME

BIT

CONTENTS

7Dh

APT_HCL

[6 : 0] Suppression level of horizontal edge signal.

7Eh

APT_VGA

[4 : 0] Initial value of APT_VGA (gain of vertical edge signal)

7Fh

APT_VCL

[6 : 0] Suppression level of vertical edge signal.

APT_S

[7 : 0] Start point of edge signal suppression (PGA gain).

81h

APT_H

[5 : 0] Gain of edge signal suppression.

APT_Y

[5 : 0] Start point of edge signal suppression in maximum PGA gained luminance.

CKI_HCL2

[7 : 0] Luminance suppression point of high luminance aperture.

CKI_ETI

[6]

Select level of edge signal, used in internal calculation. 1 : 1/4 times

[5 : 3] Delete timing of horizontal edge : –2 to +2

[2 : 0] Delete timing of vertical edge : –2 to +2

85h

LC_K1

[7 : 0] Difference of 0H, 2H signal allowed level, for judgment of line crawl.

LC_MAX

[7 : 0] Judgment of luminance level, for judgment of line crawl.

SETUP

[6]

Switch CBLK level.

[5 : 0] Adjustment of setup level (complement of 2).

89h

BAS_R

[7]

Sign of burst level R – Y 1 : – direction 0 : + direction

[6 : 0] Burst level R – Y.

8Ah

BAS_B

[7]

Sign of burst level B – Y 1 : – direction 0 : + direction

[6 : 0] Burst level B – Y (sign + absolute value).

8Bh

OUTGA

[6]

1 : Mute in encoder.

[5]

1 : Stop adding SYNC to analog output.

[4 : 0] Gain of analog output (1 time at 10h).

[7 : 0] Adjustment of SYNC level.

[7]

1 : Disable output mute at power-on.

[6 : 0] Period of mute (MUTE_OUT x 2 vertical period)

8Eh

SEL_FH

[7]

Switch attribute of FH

1 : Inverted

SEL_FR

[6]

Switch attribute of FR

1 : Inverted

SEL_ADCK

[5 : 3] ADCK phase adjustment

When using 270 k, 320 k-pixel CCDs 000 : standard to 101 : 300˚ (delayed

from "000" to "101" every 60˚.)

When using 410 k, 470 k-pixel CCDs 000 : standard to 101 : 270˚ (delayed

from "000" to "101" every 45˚.)

[2 : 0] FS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from

"000" to "111" every 2 ns.)

80h

82h

83h

84h

86h

LC_K2

[7 : 0] Difference of R, B signal allowed level, for judgment of line crawl.

87h

88h

8Ch

SYNCLEV

8Dh

MUTE_OUT

SEL_FS

8Fh

SEL_FH2

[7 : 6] FH2 phase adjustment

00 : standard 01 : 1 ns delay 10 : 2 ns delay 11 : 3 ns delay

SEL_FCDS

[5 : 3] FCDS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from

"000" to "111" every 2 ns.)

[2 : 0] RS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from

"000" to "111" every 2 ns.)

[6]

1 : Standby

[5 : 0] Period of return from standby (STANDBY x vertical period)

SEL_RS

90h

STANDBY

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