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LPC1102 Datasheet(PDF) 21 Page - NXP Semiconductors

Part # LPC1102
Description  32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM
PDF  39 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC1102 Datasheet(HTML) 21 Page - NXP Semiconductors

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LPC1102
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2011
21 of 39
NXP Semiconductors
LPC1102
32-bit ARM Cortex-M0 microcontroller
9.1 BOD static characteristics
[1]
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC1102
user manual.
9.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC1102 user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIOnDATA registers to drive the outputs LOW.
Table 7.
BOD static characteristics[1]
Tamb =25 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage
interrupt level 0
assertion
-
1.65
-
V
de-assertion
-
1.80
-
V
interrupt level 1
assertion
-
2.22
-
V
de-assertion
-
2.35
-
V
interrupt level 2
assertion
-
2.52
-
V
de-assertion
-
2.66
-
V
interrupt level 3
assertion
-
2.80
-
V
de-assertion
-
2.90
-
V
reset level 0
assertion
-
1.46
-
V
de-assertion
-
1.63
-
V
reset level 1
assertion
-
2.06
-
V
de-assertion
-
2.15
-
V
reset level 2
assertion
-
2.35
-
V
de-assertion
-
2.43
-
V
reset level 3
assertion
-
2.63
-
V
de-assertion
-
2.71
-
V



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