LPC1102 datasheet(13/39 Pages) NXP

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LPC1102

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Product data sheet

Rev. 4 — 24 June 2011

13 of 39

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

following a chip reset and may be enabled by software. The program must configure and

activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100

s.

7.14.3 Wake-up process

The LPC1102 begins operation at power-up by using the 12 MHz IRC oscillator as the

clock source. This allows chip operation to resume quickly. If an external clock or the PLL

is needed by the application, software will need to enable these features and wait for them

to stabilize before they are used as a clock source.

7.14.4 Power control

The LPC1102 supports a variety of power control features. There are two special modes

of processor power reduction: Sleep mode and Deep-sleep mode. The CPU clock rate

may also be controlled as needed by changing clock sources, reconfiguring PLL values,

and/or altering the CPU clock divider value. This allows a trade-off of power versus

processing speed based on application requirements. In addition, a register is provided for

shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power

consumption by eliminating all dynamic power use in any peripherals that are not required

for the application. Selected peripherals have their own clock divider which provides even

better power control.

7.14.4.1

Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through a simple call to the power profiles. The power configuration routine configures the

LPC1102 for one of the following power modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profiles includes a routine to select the optimal PLL settings for a

given system clock and PLL input clock.

7.14.4.2

Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.14.4.3

Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut

down except for the watchdog oscillator and the BOD circuit, which can be configured to

remain running in Deep-sleep mode to allow a reset initiated by a timer or BOD event.

Deep-sleep mode allows for additional power savings.

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