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STM32F407IG Datasheet(PDF) 60 Page - STMicroelectronics |
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STM32F407IG Datasheet(HTML) 60 Page - STMicroelectronics |
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60 / 154 page ![]() Electrical characteristics STM32F405xx, STM32F407xx 60/154 Doc ID 022152 Rev 1 Table 11. Limitations depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency (fFlashmax) Number of wait states at maximum CPU frequency(1) I/O operation FSMC controller operation Possible Flash memory operations VDD =1.8 to 2.1 V(2) Conversion time up to 1.2 Msps 16 MHz with no Flash memory wait state TBD – Degraded speed performance – No I/O compensation up to 30 MHz 8-bit erase and program operations only VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps 18 MHz with no Flash memory wait state 7(3) – Degraded speed performance – No I/O compensation up to 30 MHz 16-bit erase and program operations VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps 24 MHz with no Flash memory wait state 6(3) – Degraded speed performance – I/O compensation works up to 48 MHz 16-bit erase and program operations VDD = 2.7 to 3.6 V(4) Conversion time up to 2.4 Msps 30 MHz with no Flash memory wait state 5(3) – Full-speed operation – I/O compensation works –up to 60 MHz when VDD = 3.0 to 3.6 V –up to 48 MHz when VDD = 2.7 to 3.0 V 32-bit erase and program operations 1. The number of wait states can be reduced by reducing the CPU frequency. 2. If PDR_ON is set to VSS, this value can be lowered to 1.7 V when the device operates in a reduced temperature range (0 to 70 °C). 3. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution. 4. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V. |
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