STM32F407IG datasheet(85/154 Pages) STMICROELECTRONICS

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STM32F405xx, STM32F407xx

Electrical characteristics

Doc ID 022152 Rev 1

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A device reset allows normal operations to be resumed.

The test results are given in Table 38. They are based on the EMS levels and classes

defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

●

Corrupted program counter

●

Unexpected reset

●

Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Table 38.

EMS characteristics

Symbol

Parameter

Conditions

Level/

Class

VFESD

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

VDD = 3.3 V, LQFP100, TA = +25 °C,

fHCLK = 84 MHz, conforms to

IEC 61000-4-2

VEFTB

Fast transient voltage burst limits to be

applied through 100 pF on VDD and VSS

pins to induce a functional disturbance

VDD = 3.3 V, LQFP100, TA = +25 °C,

fHCLK = 84 MHz, conforms to

IEC 61000-4-2

STM32F407IG Datasheet(PDF) 85 Page - STMicroelectronics

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