STM32F407IG datasheet(92/154 Pages) STMICROELECTRONICS

92 / 154 page

Electrical characteristics

STM32F405xx, STM32F407xx

92/154

Doc ID 022152 Rev 1

5.3.17

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, RPU (see Table 43).

Unless otherwise specified, the parameters given in Table 46 are derived from tests

performed under the ambient temperature and VDD supply voltage conditions summarized

in Table 10.

Figure 29.

Recommended NRST pin protection

The reset network protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 46. Otherwise the reset is not taken into account by the device.

Table 46.

NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL(NRST)

(1)

Guaranteed by design, not tested in production.

NRST Input low level voltage

–0.5

0.8

VIH(NRST)

(1)

NRST Input high level voltage

VDD+0.5

Vhys(NRST)

NRST Schmitt trigger voltage

hysteresis

200

RPU

Weak pull-up equivalent resistor(2)

The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution

to the series resistance must be minimum

(~10% order)

VIN = VSS

VF(NRST)

(1)

NRST Input filtered pulse

100

VNF(NRST)

(1)

NRST Input not filtered pulse

VDD > 2.7 V

300

TNRST_OUT Generated reset pulse duration

Internal

Reset source

µs

STM32F407IG Datasheet(PDF) 92 Page - STMicroelectronics

STM32F407IG Datasheet(HTML) 92 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL