AD9628 datasheet(9/44 Pages) AD

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AD9628

Rev. 0 | Page 9 of 44

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Limit

Unit

SYNC TIMING

REQUIREMENTS

SSYNC

SYNC to rising edge of CLK+ setup time

0.24

ns typ

HSYNC

SYNC to rising edge of CLK+ hold time

0.40

ns typ

SPI TIMING

REQUIREMENTS

Setup time between the data and the rising edge of SCLK

ns min

Hold time between the data and the rising edge of SCLK

ns min

CLK

Period of the SCLK

ns min

Setup time between CSB and SCLK

ns min

Hold time between CSB and SCLK

ns min

HIGH

SCLK pulse width high

ns min

LOW

SCLK pulse width low

ns min

EN_SDIO

Time required for the SDIO pin to switch from an input to an output relative

to the SCLK falling edge

ns min

DIS_SDIO

Time required for the SDIO pin to switch from an output to an input relative

to the SCLK rising edge

ns min

Timing Diagrams

tPD

tSKEW

tCH

tDCO

tCLK

N – 16

N – 17

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

N – 15

N – 14

N – 13

N – 12

VIN

CLK+

CLK–

CH A/CH B DATA

DCOA/DCOB

Figure 2. CMOS Default Output Mode Data Output Timing

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