AD9628 datasheet(30/44 Pages) AD

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AD9628

Rev. 0 | Page 30 of 44

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR from the low fre-

quency SNR (SNRLF) at a given input frequency (fINPUT) due to

jitter (tJRMS) can be calculated by

SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10

)

(

SNR

−

]

In the previous equation, the rms aperture jitter represents the

clock input jitter specification. IF undersampling applications

are particularly sensitive to jitter, as illustrated in Figure 59.

100

FREQUENCY (MHz)

0.5ps

0.2ps

0.05ps

1.0ps

1.5ps

2.0ps

2.5ps

3.0ps

Figure 59. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9628.

To avoid modulating the clock signal with digital noise, keep

power supplies for clock drivers separate from the ADC output

driver supplies. Low jitter, crystal-controlled oscillators make the

best clock sources. If the clock is generated from another type of

source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

See the AN-501 Application Note and the AN-756 Application

Note available on www.analog.com for more information.

CHANNEL/CHIP SYNCHRONIZATION

The AD9628 has a SYNC input that offers the user flexible

synchronization options for synchronizing sample clocks

across multiple ADCs. The input clock divider can be enabled

to synchronize on a single occurrence of the SYNC signal or on

every occurrence. The SYNC input is internally synchronized

to the sample clock; however, to ensure that there is no timing

uncertainty between multiple parts, the SYNC input signal should

be externally synchronized to the input clock signal, meeting the

setup and hold times shown in Table 5. Drive the SYNC input

using a single-ended CMOS-type signal.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 60, the analog core power dissipated by

the AD9628 is proportional to its sample rate. The digital

power dissipation of the CMOS outputs are determined

primarily by the strength of the digital drivers and the load

on each output bit.

The maximum DRVDD current (IDRVDD) can be calculated as

IDRVDD = VDRVDD × CLOAD × fCLK × N

where N is the number of output bits (26, in the case of the

AD9628).

This maximum current occurs when every output bit switches

on every clock cycle, that is, a full-scale square wave at the Nyquist

frequency of fCLK/2. In practice, the DRVDD current is estab-

lished by the average number of output bits switching, which

is determined by the sample rate and the characteristics of the

analog input signal.

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data in Figure 60 was

taken in CMOS mode using the same operating conditions as those

used for the power supplies and power consumption specifications

in Table 1 with a 5 pF load on each output driver.

100

140

190

240

105

125

ENCODE RATE (MSPS)

IAVDD

IDRVDD

TOTAL POWER

Figure 60. AD9628-125 Power and Current vs. Clock Rate (1.8 V CMOS

Output Mode)

100

120

140

160

180

200

105

ENCODE RATE (MSPS)

IAVDD

IDRVDD

TOTAL POWER

Figure 61. AD9648-105 Power and Current vs. Clock Rate (1.8 V CMOS

Output Mode)

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