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HT67F60 Datasheet(PDF) 177 Page - Holtek Semiconductor Inc

Part # HT67F60
Description  TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM
PDF  242 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 177 Page - Holtek Semiconductor Inc

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HT67F30/HT67F40/HT67F50/HT67F60
TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM
Rev. 1.50
176
March 06 , 2012
Rev. 1.50
177
March 06 , 2012
I2C Bus Data and Acknowledge Signal
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged
receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.
After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it
can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal
from the master receiver, then the slave transmitter will release the SDA line to allow the master to
send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD
register. If setup as a transmitter, the slave device must first write the data to be transmitted into the
SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD
register.
When the slave receiver receives the data byte, it must generate an acknowledge bit, known as
TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit
in the SIMC1 register to determine if it is to send another data byte, if not then it will release the
SDA line and await the receipt of a STOP signal from the master.
I2C Communication Timing Diagram
Da ta
10
1
00
1
0
0
1
0
01010
1
1
S= St ar t (1 b it )
SA =S la ve A dd re ss (7 b it s)
SR =S RW b i t ( 1 bi t)
M= Sl av e dev ic e s end a ck now l edge bi t (1 b it )
D= Da ta ( 8 bi ts )
A= AC K ( RX AK b i t f or tr ans mi tte r, T XAK b i t f or r ec ei ve r 1 bi t)
P= St op (1 b it )
SC L
St ar t
SD A
SR W
AC K
AC K
St op
SC L
SD A
Sl av e Ad dr es s
SS AS R
MD
A
DA
SS AS R
MD
A
DA
P
Note: *When a slave address is matched, the device must be placed in either
the transmit mode and then write data to the SIMD register, or in the
receive mode where it must implement a dummy read from the SIMD
register to release the SCL line.



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