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HT67F60 Datasheet(PDF) 180 Page - Holtek Semiconductor Inc |
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HT67F60 Datasheet(HTML) 180 Page - Holtek Semiconductor Inc |
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180 / 242 page  Rev. 1.50 180 March 06 , 2012 Rev. 1.50 181 March 06 , 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO There are several configuration options associated with the SPIA interface. One of these is to enable the SPIA function which selects the SPIA pins rather than normal I/O pins. Note that if the configuration option does not select the SPIA function then the SPIAEN bit in the SPIAC0 register will have no effect. Another two SPIA configuration options determine if the SACSEN and SAWCOL bits are to be used. SPIA Registers There are three internal registers which control the overall operation of the SPIA interface. These are the SPIAD data register and two registers SPIAC0 and SPIAC1. Register Name Bit 7 6 5 4 3 2 1 0 SPIAC0 SASPI2 SASPI1 SASPI0 — — — SPIAEN — SPIAC1 — — SACKPOL SACKEG SAMLS SACSEN SAWCOL SATRF SPIAD D7 D6 D5 D4 D3 D2 D1 D0 SPIA Registers List The SPIAD register is used to store the data being transmitted and received. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SPIAD register. After the data is received from the SPI bus, the device can read it from the SPIAD register. Any transmission or reception of data from the SPI bus must be made via the SPIAD register. ● SPIAD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x” unknown There are also two control registers for the SPIA interface, SPIAC0 and SPIAC1. Register SPIAC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision flag etc. ● SPIAC0 Register Bit 7 6 5 4 3 2 1 0 Name SASPI2 SASPI1 SASPI0 — — — SPIAEN — R/W R/W R/W R/W — — — R/W — POR 1 1 1 0 0 0 0 0 Bit 7~5 SASPI2~SASPI0: Master/Slave Clock Select 000 : SPIA master, fSYS/4 001 : SPIA master, fSYS/16 010 : SPIA master, fSYS/64 011 : SPIA master, fSUB 100 : SPIA master, TP0 CCRP match frequency/2 (PFD) 101 : SPIA slave Bit 4~2 Unimplemented, read as “0” Bit 1 SPIAEN: SPIA enable or disable 0: Disable 1: Enable Bit 0 Unimplemented, read as “0” |
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