HT67F60 datasheet(182/242 Pages) HOLTEK

182 / 242 page

Rev. 1.50

182

March 06 , 2012

Rev. 1.50

183

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

SPIA Communication

After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when

data is written to the SPIAD register, transmission/reception will begin simultaneously. When the

data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the

application program. In the Slave Mode, when the clock signal from the master has been received,

any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into

the SPIAD register.

The master should output an SCSA signal to enable the slave device before a clock signal is

provided. The slave data to be transferred should be well prepared at the appropriate moment

relative to the SCSA signal depending upon the configurations of the SACKPOL bit and SACKEG

bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal

for various configurations of the SACKPOL and SACKEG bits.

The SPIA will continue to function even in the IDLE Mode.

SC KA ( SA CK PO L= 1, S AC KE G= 0)

SP IA EN , SA CS EN =1

SP IA EN =1 , SA CS EN =0 ( Ex te rn al P u ll- Hi gh )

SC KA ( SA CK PO L= 0, S AC KE G= 0)

SD OA ( SA CK EG =0 )

SD OA ( SA CK EG =1 )

SC SA

SD IA D at a C apt ur e

D 7/ D 0D 6/ D 1D 5/ D 2D 4/ D 3D 3/ D 4D 2/ D 5D 1/ D 6D 0/ D 7

Wr it e to S PI AD

SC KA ( SA CK PO L= 1, S AC KE G= 1)

SC KA ( SA CK PO L= 0, S AC KE G= 1)

SPIA Master Mode Timing

SC KA ( SA CK PO L= 1)

SC KA ( SA CK PO L= 0)

SD OA

SC SA

SD IA D at a C apt ur e

D7 /D 0D 6/ D1

D5 /D 2D 4/ D3 D3 /D 4D 2/ D5

D1 /D 6D 0/ D7

Wr it e to S PI AD

(S DO A does n ot c hange unt il fi rs t S CK A edge )

SPIA Slave Mode Timing – SACKEG=0

HT67F60 Datasheet(PDF) 182 Page - Holtek Semiconductor Inc

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