HT67F60 datasheet(179/242 Pages) HOLTEK

179 / 242 page

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM

Rev. 1.50

178

March 06 , 2012

Rev. 1.50

179

March 06 , 2012

SPIA Interface Operation

The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin

names SDIA, SDOA, SCKA and SCSA. Pins SDIA and SDOA are the Serial Data Input and Serial

Data Output lines, SCKA is the Serial Clock line and SCSA is the Slave Select line. As the SPIA

interface pins are pin-shared with normal I/O pins, the SPIA interface must first be enabled by

selecting the SPIA enable configuration option and setting the correct bits in the SPIAC0 and

SPIAC1 registers. After the SPIA configuration option has been configured it can also be

additionally disabled or enabled using the SPIAEN bit in the SPIAC0 register. Communication

between devices connected to the SPIA interface is carried out in a slave/master mode with all data

transfer initiations being implemented by the master. The Master also controls the clock signal. As

the device only contains a single SCSA pin only one slave device can be utilized.

The SCSA pin is controlled by the application program, set the SACSEN bit to “1” to enable the

SCSA pin function and clear the SACSEN bit to “0” to place the SCSA pin into a floating state.

SP IA M ast er

SP IA S l ave

SC KA

SD OA

SD IA

SC SA

SC KA

SD IA

SD OA

SC SA

SPIA Master/Slave Connection

Da ta B us

SP IA P in

SD OA P in

SP IA D

Tx /R x Sh if t R egi st er

Bu sy

St at us

C onf i gur at io n

Op ti on

SA TR F Fl ag

E nabl e/ Di s abl e

SAW CO L Fl ag

Cl oc k

E dge/ Po la ri ty

C ont ro l

Cl oc k

S our ce S el ec t

f SY S

f SU B

Ti me r/ Ev ent C ount er 0 out put /2 ( PF D0 )

SC KA P in

SC SA P in

C onf i gur at io n

Op ti on

SA CS EN b it

E nabl e/ Di s abl e

SA CK EG b it

SA CK PO L bi t

SPIA Block Diagram

The SPIA function in this device offers the following features:

● Full duplex synchronous data transfer

● Both Master and Slave modes

● LSB first or MSB first data transmission modes

● Transmission complete flag

● Rising or falling active clock edge

● SAWCOL and SACSEN bit enabled or disable select

The status of the SPIA interface pins is determined by a number of factors such as whether the

device is in the master or slave mode and upon the condition of certain control bits such as SACSEN

and SPIAEN.

HT67F60 Datasheet(PDF) 179 Page - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 179 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL