HT67F60 datasheet(181/242 Pages) HOLTEK

181 / 242 page

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM

Rev. 1.50

180

March 06 , 2012

Rev. 1.50

181

March 06 , 2012

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SPIAC1 Register

Bit

Name

—

SACKPOL SACKEG SAMLS SACSEN SAWCOL SATRF

R/W

POR

Bit 7~6

Unimplemented, read as “0”.

This bit can be read or written by user software program.

Bit 5

SACKPOL: Determines the base condition of the clock line

0: SCKA line will be high when the clock is inactive

1: SCKA line will be low when the clock is inactive

The SACKPOL bit determines the base condition of the clock line, if the bit is high,

then the SCKA line will be low when the clock is inactive. When the SACKPOL bit is

low, then the SCKA line will be high when the clock is inactive.

Bit 4

SACKEG: Determines the SPIA SCKA active clock edge type

SACKPOL = 0:

0: SCKA has high base level with data capture on SCKA rising edge

1: SCKA has high base level with data capture on SCKA falling edge

SACKPOL = 1:

0: SCKA has low base level with data capture on SCKA falling edge

1: SCKA has low base level with data capture on SCKA rising edge

The SACKEG and SACKPOL bits are used to setup the way that the clock signal

outputs and inputs data on the SPI bus. These two bits must be configured before a

data transfer is executed otherwise an erroneous clock edge may be generated. The

SACKPOL bit determines the base condition of the clock line, if the bit is high, then

the SCKA line will be low when the clock is inactive. When the SACKPOL bit is low,

then the SCKA line will be high when the clock is inactive. The SACKEG bit

determines active clock edge type which depends upon the condition of the SACKPOL

bit.

Bit 3

SAMLS: MSB/LSB First Bit

0: LSB shift first

1: MSB shift first

This is the data shift select bit and is used to select how the data is transferred, either

MSB orLSB first. Setting the bit high will select MSB first and low for LSB first.

Bit 2

SACSEN: Select Signal Enable/Disable Bit

0: SCSA floating

1: Enable

The SACSEN bit is used as an enable/disable for the SCSA pin. If this bit is low, then

the SCSA pin will be disabled and placed into a floating condition. If the bit is high the

SCSA pin will be enabled and used as a select pin. Note that using the SACSEN bit

can be disabled or enabled via configuration option.

Bit 1

SAWCOL: Write Collision Bit

0: Collision free

1: Collision detected

The SAWCOL flag is used to detect if a data collision has occurred. If this bit is high it

means that data has been attempted to be written to the SPIAD register during a data

transfer operation. This writing operation will be ignored if data is being transferred.

The bit can be cleared by the application program. Note that using the SAWCOL bit

can be disabled or enabled via configuration option.

Bit 0

SATRF: Transmit /Receive Flag

0: Not complete

1: Transmission/reception complete

The SATRF bit is the Transmit/Receive Complete flag and is set “1” automatically

when an SPIA data transmission is completed, but must set to zero by the application

program. It can be used to generate an interrupt.

HT67F60 Datasheet(PDF) 181 Page - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 181 Page - Holtek Semiconductor Inc

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