MICRF002 datasheet(9/17 Pages) MICREL

9 / 17 page

Micrel, Inc.

MICRF002/RF022

July 2008

M9999-070808

Step 3: Selecting the CTH Capacitor

Extraction of the dc value of the demodulated signal

for purposes of logic-level data slicing is accomplished

using the external threshold capacitor CTH and the on-

chip switched capacitor “resistor” RSC, shown in the

block diagram.

Slicing level time constant values vary somewhat with

decoder type, data pattern, and data rate, but typically

values range from 5ms to 50ms. Optimization of the

value of CTH is required to maximize range.

Selecting Capacitor CTH

The first step in the process is selection of a data-slicing-

level time constant. This selection is strongly dependent on

system issues including system decode response time and

data code structure (that is, existence of data preamble,

etc.). This issue is covered in more detail in Application

Note 22.

The effective resistance of RSC is listed in the electrical

characteristics table as 145kΩ at 315MHz, this value scales

linearly with frequency. Source impedance of the CTH pin at

other frequencies is given by Equation 4, where fT is in

MHz:

(4)

4.8970

145kΩ

τ of 5x the bit-rate is recommended. Assuming that a slicing

level time constant τ has been established, capacitor CTH

may be computed using Equation 5:

(5)

A standard ±20% X7R ceramic capacitor is generally

sufficient. Refer to Application Hint 42 for CTH and CAGC

selection examples.

Step 4: Selecting the CAGC Capacitor

The signal path has AGC (automatic gain control) to

increase input dynamic range. The attack time constant of

the AGC is set externally by the value of the CAGC capacitor

connected to the CAGC pin of the device. To maximize

system range, it is important to keep the AGC control

voltage ripple low, preferably under 10mVPP once the

control voltage has attained its quiescent value. For this

reason capacitor values of at least 0.47µF are

recommended.

The AGC control voltage is carefully managed on-chip to

allow duty-cycle operation of the MICRF002. When the

device is placed into shutdown mode (SHUT pin pulled

high), the AGC capacitor floats to retain the voltage. When

operation is resumed, only the voltage droop due to

capacitor leakage must be replenished. A relatively low-

leakage capacitor is recommended when the devices are

used in dutycycled operation.

To further enhance duty-cycled operation, the AGC push

and pull currents are boosted for approximately 10ms

immediately after the device is taken out of shutdown. This

compensates for AGC capacitor voltage droop and reduces

the time to restore the correct AGC voltage. The current is

boosted by a factor of 45.

Selecting CAGC Capacitor in Continuous Mode

A CAGC capacitor in the range of 0.47µF to 4.7µF is typically

recommended. The value of the CAGC should be selected to

minimize the ripple on the AGC control voltage by using a

sufficiently large capacitor. However if the capacitor is too

large the AGC may react too slowly to incoming signals.

AGC settling time from a completely discharged (zero-volt)

state is given approximately by Equation 6:

(6)

0.44

1.333C

∆t

AGC −

where:

CAGC sin in µF, and ∆t is in seconds.

Selecting CAGC Capacitor in Duty-Cycle Mode

Voltage droop across the CAGC capacitor during shutdown

should be replenished as quickly as possible after the IC is

enabled. As mentioned above, the MICRF002 boosts the

push-pull current by a factor of 45 immediately after start-

up. This fixed time period is based on the reference

oscillator frequency fT. The time is 10.9ms for fT = 6.00MHz,

and varies inversely with fT. The value of CAGC capacitor

and the duration of the shutdown time period should be

selected such that the droop can be replenished within this

10ms period.

Polarity of the droop is unknown, meaning the AGC voltage

could droop up or down. Worst-case from a recovery

standpoint is downward droop, since the AGC pull-up

current is 1/10th magnitude of the pulldown current. The

downward droop is replenished according to the Equation

(7)

∆t

∆V

AGC

where:

I = AGC pullup current for the initial 10ms (67.5µA)

CAGC = AGC capacitor value

∆t = droop recovery time

∆V = droop voltage

For example, if user desires ∆t = 10ms and chooses a

4.7µF CAGC, then the allowable droop is about 144mV.

Using the same equation with 200nA worst case pin

leakage and assuming 1µA of capacitor leakage in the

same direction, the maximum allowable ∆t (shutdown time)

is about 0.56s for droop recovery in 10ms.

The ratio of decay-to-attack time-constant is fixed at 10:1

(that is, the attack time constant is 1/10th of the decay time

constant). Generally the design value of 10:1 is adequate

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