MICRF002 datasheet(13/17 Pages) MICREL

13 / 17 page

Micrel, Inc.

MICRF002/RF022

July 2008

M9999-070808

CAGC Pin

VDDBB

VSSBB

675µA

67.5µA

Compa-

rator

1.5µA

15µA

Timout

CAGC

Figure 3. CAGC Pin

Figure 3 illustrates the CAGC pin interface circuit. The AGC

control voltage is developed as an integrated current into a

capacitor CAGC. The attack current is nominally 15µA, while

the decay current is a 1/10th scaling of this, nominally

1.5µA, making the attack/decay time constant ratio a fixed

10:1. Signal gain of the RF/IF strip inside the IC diminishes

as the voltage at CAGC decreases. Modification of the

attack/decay ratio is possible by adding resistance from the

CAGC pin to either VDDBB or VSSBB, as desired.

Both the push and pull current sources are disabled during

shutdown, which maintains the voltage across CAGC, and

improves recovery time in duty-cycled applications. To

further improve duty-cycle recovery, both push and pull

currents are increased by 45 times for approximately 10ms

after release of the SHUT pin. This allows rapid recovery of

any voltage droop on CAGC while in shutdown.

DO and WAKEB Pins

VDDBB

VSSBB

Compa-

rator

10µA

Figure 4. DO and WAKEB Pins

The output stage for DO (digital output) and WAKEB

(wakeup output) is shown in Figure 4. The output is a 10µA

push and 10µA pull switched-current stage. This output

stage is capable of driving CMOS loads. An external buffer-

driver is recommended for driving high-capacitance loads.

REFOSC Pin

250

200k

Active

Bias

REFOSC

30pF

30µA

VDDBB

VSSBB

Figure 5. REFOSC Pin

The REFOSC input circuit is shown in Figure 5. Input

impedance is high (200kΩ). This is a Colpitts oscillator with

internal 30pF capacitors. This input is intended to work with

standard ceramic resonators connected from this pin to the

VSSBB pin, although a crystal may be used when greater

frequency accuracy is required. The nominal dc bias

voltage on this pin is 1.4V.

SEL0, SEL1, SWEN, and SHUT Pins

to Internal

Circuits

VDDBB

VSSBB

SEL0,

SEL1,

SWEN

VSSBB

SHUT

Figure 6a. SEL0, SEL1, SWEN Pins

to Internal

Circuits

VDDBB

VSSBB

SHUT

VSSBB

Figure 6b. SHUT Pin

Control input circuitry is shown in Figures 6a and 6b. The

standard input is a logic inverter constructed with minimum

geometry MOSFETs (Q2, Q3). P-channel MOSFET Q1 is

a large channel length device which functions essentially

as a “weak” pullup to VDDBB. Typical pull-up current is 5µA,

leading to an impedance to the VDDBB supply of typically

1MΩ.

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