PSB7280 datasheet(21/190 Pages) SIEMENS

21 / 190 page

PSB 7280

Semiconductor Group

Data Sheet 1998-07-01

General Architecture and Functions

2.1

Architecture

Figure 6 shows a sketch of the PSB 7280 architecture with its most important functional

modules.

Figure 6

The audio processing of the PSB 7280 is based on a 16-bit fixed point DSP core, SPCF

(Signal Processor Core Fast).

The Clock Generator is responsible for generating the internal clocks for the SPCF. A

Baud Rate Generator provides an output clock of programmable rate.

The Parallel Host Interface is used to control the circuit through an associated host via

interrupt handshake procedures. Alternatively, the circuit can be controlled via the serial

audio

interface,

thus

enabling

standalone

applications

implemented.

Communication between the host, if used, and the DSP is interrupt supported, via a full-

duplex 256-byte on-chip Communication Memory Mailbox.

Mailbox

256 byte

IOM/

PCM

Serial

Audio

I/F

Mon, C/I

Control

DSP

Cor e

SC LK

RFS

TFS

DCL

FSC

Re se t

C A(0 :15 )

C D(0 :15)

CWR#

C RD#

CDS#

XTA L1

CL KO

C PS#

CS#

AD(0 :7)

WR#

RD#

AL E

8 K W dat a

X-RO M

INTR#

XTA L2

EA#

IN T#

SIO

2 K W dat a

X-RA M

32 KW program

ROM

Audio

HDLC 1

HDLC 2

Rec 1

Trm 1

Rec 2

Trm 2

1 K W data

Y-RA M

CM1

Tim ers

Mailbox

256 by te

1 K W data

X-RA M

Confi g/ Control

Regis ters

BRG

clock

gen/

PLL

External Memor y Interface

Parallel Host Interface

A(0 :3)

GP(0:3 )

GPIO

I/F

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