PSB7280 datasheet(39/190 Pages) SIEMENS

39 / 190 page

PSB 7280

Semiconductor Group

Data Sheet 1998-07-01

Interrupt from DSP to Host

For a soft interrupt from the DSP to the host, the procedure is identical. In this case, the

soft interrupt is a maskable interrupt on line INT. The interrupt vector is written by the

DSP in address 3058

H (IND). Simultaneously, the Interrupt DSP Busy bit INDB (address

H, writable by host) is set to ‘1’. Having recognized an IND interrupt status, the host

reads address 58

H (IND), which automatically resets the DINT interrupt status bit in the

Host Interrupt Status Register for INT (address 75

H). The INDB bit can be written by the

host again to ‘0’ to indicate that it is ready to accept a new interrupt from the DSP. The

16-bit control register located at 60/61

H (3060/3061H) may contain additional information

for the host to read after an IND interrupt.

Please refer to the specific interface

procedures for details.

Registers for Accessing the External Memory

In normal operation, the program bus of the DSP is connected via the external memory

interface to the external memory bus so that instructions are fetched from an external

memory when an address between 8000

H and FFFFH is hit, if EA=“High”. If EA=“Low”,

the whole address range is for off-chip programs.

If the bit LDMEM (see description of Configuration and Control Registers, Chapter 4) is

set to ‘1’ and bit DACC is ‘0’ (see description of Configuration and Control Registers,

Chapter 5.3), the external memory interface address and data buses are connected to

the outputs of registers address low/high (at host address 44/45

H) and data low/high (at

host address 46/47

H), respectively. This feature can be used to down-load programs into

a memory connected to the PSB 7280.

When a write access to the data high register (address 47

H) is detected, this activates

the external memory interface write signal CWR for the duration of the host WR signal

(independent of any possible wait states in NRW(3:0)). Thus the host writes one word of

data into an external memory by effecting the following write operations:

Write Address Low + High

Write Data Low

Write Data High (operation is carried out during this write cycle).

When LDMEM is ‘1’, the CPS signal is permanently active.

Note: When LDMEM is ‘0’, the CPS signal is activated when a read access - program

fetch - is performed on the external memory interface.

Registers Pertaining to the Mailbox

The function of these host registers is described in detail in the next section.

Hardware Interrupt Registers

In the following the interrupts for the host are listed, as well as, for completeness, those

for the embedded DSP.

PSB7280 Datasheet(PDF) 39 Page - Siemens Semiconductor Group

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