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CDCM9102 Datasheet(PDF) 5 Page - Texas Instruments

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Part # CDCM9102
Description  Low-Noise Two-Channel 100-MHz Clock Generator
PDF  22 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDCM9102 Datasheet(HTML) 5 Page - Texas Instruments

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CDCM9102
www.ti.com
SCAS922
– FEBRUARY 2012
CRYSTAL-OSCILLATOR INPUT-PORT CHARACTERISTICS (XIN)
VDD = 3.3 V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CRYSTAL CHARACTERISTICS (External 25 MHz Crystal)
fXTAL
Crystal input frequency
Fundamental mode
25
MHz
ESR
Effective series resistance of crystal
50
Ω
CIN
On-chip load capacitance
8
10
pF
XTALDL
Maximum drive level - XTAL
0.1
1
mW
CSHUNT
Maximum shunt capacitance
7
pF
CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = LVPECL)
VDD1, VDD2 = 3.3 V; TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
Output high voltage
VDD – 1.18
VDD – 0.73
V
VOL
Output low voltage
VDD – 2
VDD – 1.55
V
|VOD|
Differential output voltage
0.6
1.23
V
tR/tF
Output rise/fall time
20% to 80%
175
ps
ODC
Output duty cycle
45%
55%
tSKEW
Skew between outputs
20
ps
CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = LVDS)
VDD1, VDD2 = 3.3V; TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
|VOD|
Differential output voltage
0.247
0.454
V
ΔVOD
VOD magnitude change
50
mV
VOS
Common-mode voltage
1.125
1.375
V
ΔVOS
VOS magnitude change
50
mV
tR/tF
Output rise/fall time
20% to 80%
255
ps
ODC
Output duty cycle
45%
55%
tSKEW
Skew between outputs
30
ps
CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = LVCMOS)
VDD1, VDD2 = 3.3V; TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
Output high voltage
VCC = 3 V to 3.6 V, IOH = –100 µA
VDD – 0.5
V
VOL
Output low voltage
VCC = 3 V to 3.6 V, IOH = 100 µA
0.3
V
tSLEW
Output rise/fall slew rate
20% to 80%
2.4
V/ns
ODC
Output duty cycle
45%
55%
tSKEW
Skew between outputs
50
ps
OUTPUT JITTER PERFORMANCE
fOUT = 100 MHz, VDD = 3.3 V, TA = 25°C, jitter integration bandwidth 10 kHz–20 MHz
LVCMOS OUTPUT MODE
LVPECL OUTPUT MODE
LVDS OUTPUT MODE
Random jitter
Period jitter
Random jitter
Period jitter
Random jitter
Period jitter
(fs)
(ps pk-pk)
(fs)
(ps pk-pk)
(fs)
(ps pk-pk)
507
24.5
510
20.7
533
26.5
Copyright
© 2012, Texas Instruments Incorporated
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5
Product Folder Link(s): CDCM9102



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